ATTINY28L_14 Datasheet, PDF (38/81 Pages) ATMEL Corporation – High-performance and Low-power RISC Architecture

1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must
be written to WDE even though it is set to one before the disable operation starts.
2. Within the next four clock cycles, write a logical “0” to WDE. This disables the
Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0
The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the
Watchdog Timer is enabled. The different prescaling values and their corresponding
time-out periods are shown in Table 15.
Table 15. Watchdog Timer Prescale Select
WDP2
0
WDP1
0
WDP0
0
Number of WDT
Oscillator
Cycles
16K cycles
Typical
Time-out at
V_CC = 2.0V
0.15 s
Typical
Time-out at
V_CC = 3.0V
47 ms
Typical
Time-out at
V_CC = 5.0V
15 ms
0
0
1 32K cycles
0.30 s
94 ms
30 ms
0
1
0 64K cycles
0.60 s
0.19 s
60 ms
0
1
1 128K cycles
1.2 s
0.38 s
0.12 s
1
0
0 256K cycles
2.4 s
0.75 s
0.24 s
1
0
1 512K cycles
4.8 s
1.5 s
0.49 s
1
1
0 1,024K cycles
9.6 s
3.0 s
0.97 s
1
Note:
1
1 2,048K cycles
19 s
6.0 s
1.9 s
The frequency of the Watchdog oscillator is voltage-dependent, as shown in the section
“Typical Characteristics” on page 57.
The WDR (Watchdog Reset) instruction should always be executed before the Watchdog
Timer is enabled. This ensures that the reset period will be in accordance with the
Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the
Watchdog Timer may not start counting from zero.
38 ATtiny28L/V
1062F–AVR–07/06