ATTINY28L_14 Datasheet, PDF (36/81 Pages) ATMEL Corporation – High-performance and Low-power RISC Architecture

Timer Counter 0 – TCNT0
• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0
The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0.
Table 14. Clock 0 Prescale Select
CS02
CS01
CS00 Description
0
0
0
Stop, the Timer/Counter0 is stopped.
0
0
1
CK
0
1
0
Modulator Period
0
1
1
CK/64
1
0
0
CK/256
1
0
1
CK/1024
1
1
0
External Pin T0, falling edge
1
1
1
External Pin T0, rising edge
The Stop condition provides a Timer Enable/Disable function. The CK down divided
modes are scaled directly from the CK oscillator clock. If the external pin modes are
used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if the pin is
configured as an output. This feature can give the user software control of the counting.
Bit
$03
Read/Write
Initial Value
7
6
MSB
R/W
R/W
0
0
5
R/W
0
4
R/W
0
3
R/W
0
2
R/W
0
1
R/W
0
0
LSB
R/W
0
TCNT0
The Timer/Counter0 is realized as an up-counter with read and write access. If the
Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues
counting in the timer clock cycle following the write operation.
36 ATtiny28L/V
1062F–AVR–07/06