ATTINY28L_14 Datasheet, PDF (20/81 Pages) ATMEL Corporation – High-performance and Low-power RISC Architecture

Interrupts
Reset and Interrupt
Interrupt Handling
The ATtiny28 provides five different interrupt sources. These interrupts and the reset
vector each have a separate program vector in the program memory space. All the inter-
rupts are assigned to individual enable bits. In order to enable the interrupt, both the
individual enable bit and the I-bit in the status register (SREG) must be set to one.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 7. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
Table 7. Reset and Interrupt Vectors
Vector
No.
Program
Address
Source
1
$000
RESET
2
$001
INT0
3
$002
INT1
4
$003
Input Pins
5
$004
TIMER0,
OVF0
6
$005
ANA_COMP
Interrupt Definition
Hardware Pin, Power-on Reset and
Watchdog Reset
External Interrupt Request 0
External Interrupt Request 1
Low-level Input on Port B
Timer/Counter0 Overflow
Analog Comparator
The most typical and general program setup for the Reset and Interrupt vector
addresses are:
Address Labels Code
Comments
$000
rjmp
RESET
; Reset handler
$001
rjmp
EXT_INT0
; IRQ0 handler
$002
rjmp
EXT_INT1
; IRQ1 handler
$003
rjmp
LOW_LEVEL
; Low level input handler
$004
rjmp
TIM0_OVF
; Timer0 overflow handle
$005
rjmp
ANA_COMP
; Analog Comparator handle
;
$006
MAIN: <instr> xxx
; Main program start
…
…
…
…
The ATtiny28 has one 8-bit Interrupt Control Register (ICR).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the program counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
20 ATtiny28L/V
1062F–AVR–07/06