AT87C5112_14 Datasheet, PDF (38/97 Pages) ATMEL Corporation – Hardware Watchdog Timer with Reset-out

AT8xC5112
Functional Description Figure 13 shows a detailed structure of the SPI module.
Figure 2. SPI Module Block Diagram
Internal Bus
CkIdle
SPDAT
Shift Register
7 654 3210
/2
Clock
/4
/8
Divider
/16
/32
/64
/128
External Clk
Clock
Select
Receive Data Register
Clock
Logic
Pin
Control
Logic
M
S
MOSI
MISO
SCK
SS
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
SPI Interrupt Request
SPI
Control
8-bit Bus
1-bit Signal
Operating Modes
SPSTA
SPIF WCOL ^- MODF ^-
-
--
The Serial Peripheral Interface can be configured as Master mode only. The configura-
tion and initialization of the SPI module is made through one register:
• The Serial Peripheral CONtrol register (SPCON)
Once the SPI is configured, the data exchange is made using:
• SPCON
• The Serial Peripheral STAtus register (SPSTA)
• The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and
received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sam-
pling on the two serial data lines (MOSI and MISO).
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 14).
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