AT87C5112_14 Datasheet, PDF (37/97 Pages) ATMEL Corporation – Hardware Watchdog Timer with Reset-out

Baud Rate
pins (see Figure 12). To prevent bus conflicts on the MISO line, only one slave should
be selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (see Error Conditions).
In Master mode, the baud rate can be selected from a baud rate generator which is con-
troled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is
chosen from one of seven clock rates resulting from the division of the internal clock by
2, 4, 8, 16, 32, 64 or 128, or an external clock.
Table 28 gives the different clock rates selected by SPR2:SPR1:SPR0.
Table 1. SPI Master Baud Rate Selection
SPR2:SPR1:SPR0
000
001
010
011
100
101
110
111
Clock Rate
F_CkIdle /2
F_CkIdle /4
F_CkIdle/8
F_CkIdle/16
F_CkIdle /32
F_CkIdleH /64
F_CkIdle /128
External clock
Baud Rate Divisor (BD)
2
4
8
16
32
64
128
Output of BRG
35 AT8xC5112
4191C–8051–02/08