ATXMEGA32A4_14 Datasheet, PDF (36/108 Pages) ATMEL Corporation – Non-volatile Program and Data Memories

XMEGA A4
20. TWI - Two-Wire Interface
20.1 Features
20.2 Overview
• Two Identical TWI peripherals
• Simple yet Powerful and Flexible Communication Interface
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space Allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Slew-rate Limited Output Drivers
• Noise Suppression Circuitry Rejects Spikes on Bus Lines
• Fully Programmable Slave Address with General Call Support
• Address Recognition Causes Wake-up when in Sleep Mode
• I²C and System Management Bus (SMBus) compatible
The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock
(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 indi-
vidually addressable devices. Since it is a multi-master bus, one or more devices capable of
taking control of the bus can be connected.
The only external hardware needed to implement the bus is a single pull-up resistor for each of
the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE,
respectively.
8069R–AVR–06/2013
36
Not recommended for new designs -
Use XMEGA A4U series