ATXMEGA32A4_14 Datasheet, PDF (25/108 Pages) ATMEL Corporation – Non-volatile Program and Data Memories

XMEGA A4
14. PMIC - Programmable Multi-level Interrupt Controller
14.1 Features
14.2 Overview
• Separate interrupt vector for each interrupt
• Short, predictable interrupt response time
• Programmable Multi-level Interrupt Controller
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
• Interrupt vectors can be moved to the start of the Boot Section
XMEGA A4 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both low-
and medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
14.3 Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA A4 devices are shown
in Table 14-1. Offset addresses for each interrupt available in the peripheral are described for
each peripheral in the XMEGA A manual. For peripherals or modules that have only one inter-
rupt, the interrupt vector is shown in Table 14-1. The program address is the word address.
Table 14-1. Reset and Interrupt Vectors
Program Address
(Base Address)
Source
0x000
RESET
0x002
OSCF_INT_vect
0x004
PORTC_INT_base
0x008
PORTR_INT_base
0x00C
DMA_INT_base
0x014
RTC_INT_base
0x018
TWIC_INT_base
0x01C
TCC0_INT_base
0x028
TCC1_INT_base
0x030
SPIC_INT_vect
0x032
USARTC0_INT_base
0x038
USARTC1_INT_base
0x03E
AES_INT_vect
Interrupt Description
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interrupt base
DMA Controller Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
Timer/Counter 1 on port C Interrupt base
SPI on port C Interrupt vector
USART 0 on port C Interrupt base
USART 1 on port C Interrupt base
AES Interrupt vector
8069R–AVR–06/2013
25
Not recommended for new designs -
Use XMEGA A4U series