ATXMEGA32A4_14 Datasheet, PDF (14/108 Pages) ATMEL Corporation – Non-volatile Program and Data Memories

XMEGA A4
7.7 Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) give the page number and the least significant address bits (FWORD)
give the word in the page.
Devices
ATxmega16A4
ATxmega32A4
ATxmega64A4
ATxmega128A4
Table 7-2. Number of words and Pages in the Flash.
Flash
Page Size
FWORD
FPAGE
Application
Size
(words)
Size
No of Pages
16 KB + 4 KB
128
Z[6:0]
Z[13:7]
16 KB
64
32 KB + 4 KB
128
Z[6:0]
Z[14:7]
32 KB
128
64 KB + 4 KB
128
Z[6:0]
Z[15:7]
64 KB
128
128 KB + 8 KB
256
Z[7:0]
Z[16:8]
128 KB
256
Boot
Size
No of Pages
4 KB
16
4 KB
16
4 KB
16
8 KB
16
Devices
ATxmega16A4
ATxmega32A4
ATxmega64A4
ATxmega128A4
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA A4 devices.
EEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give
the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3.
EEPROM
Size
1 KB
1 KB
2 KB
2 KB
Number of Bytes and Pages in the EEPROM.
Page Size
E2BYTE
E2PAGE
(Bytes)
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
32
ADDR[4:0]
ADDR[10:5]
No of Pages
32
32
64
64
8069R–AVR–06/2013
14
Not recommended for new designs -
Use XMEGA A4U series