SAM7SE32_14 Datasheet, PDF (355/682 Pages) ATMEL Corporation – Internal High-speed Flash

SAM7SE512/256/32
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See Figure 32-9. When a multiple data byte read is
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See Figure 32-10. For Internal Address usage see Section 32.7.6.
Figure 32-9. Master Read with One Data Byte
TWD
S
DADR
RA
DATA
NP
TXCOMP
RXRDY
Write START &
STOP Bit
Read RHR
Figure 32-10. Master Read with Multiple Data Bytes
TWD S
DADR
RA
DATA n
A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P
TXCOMP
RXRDY
Write START Bit
Read RHR
DATA n
Read RHR
DATA (n+1)
Read RHR
DATA (n+m)-1
Read RHR
DATA (n+m)
Write STOP Bit
after next-to-last data read
32.7.6
Internal Address
The TWI interface can perform various transfer formats: Transfers with 7-bit slave address
devices and 10-bit slave address devices.
32.7.6.1
7-bit Slave Addressing
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 32-12. See
Figure 32-11 and Figure 32-13 for Master Write operation with internal address.
The three internal address bytes are configurable through the Master Mode register
(TWI_MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
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