SAM7SE32_14 Datasheet, PDF (183/682 Pages) ATMEL Corporation – Internal High-speed Flash

SAM7SE512/256/32
22.6.7.2
Accesses with Setup and Hold
Figure 22-32 and Figure 22-33 show an example of read and write accesses with Setup and
Hold Cycles.
Figure 22-32. Read Accesses in Standard Read Protocol with Setup and Hold⁽¹⁾
MCK
A[22:1] 00d2b
A0/NLB
00028
00d2c
NRD
NWR0/NWE
NWR1/NUB
NCS
Setup
Hold
Setup
D[15:0]
e59f
0001
0002
Note: 1. Read access, memory data bus width = 8, RWSETUP = 1, RWHOLD = 1,WSEN= 1, NWS = 0
Figure 22-33. Write Accesses with Setup and Hold⁽¹⁾
MCK
A[22:1]
008cb
00082
Hold
008cc
A0/NLB
NRD
NWR0/NWE
NWR1/NUB
NCS
D[15:0] 3000
e3a0
Setup
0605
Hold
Setup
0606
Hold
Note: 1. Write access, memory data bus width = 8, RWSETUP = 1, RWHOLD = 1, WSEN = 1, NWS = 0
6222H–ATARM–25-Jan-12
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