SAM7SE32_14 Datasheet, PDF (197/682 Pages) ATMEL Corporation – Internal High-speed Flash

SAM7SE512/256/32
• DBW: Data Bus Width
DBW
0
0
0
1
1
0
1
1
Data Bus Width
Reserved
16-bit
8-bit
Reserved
• DRP: Data Read Protocol
0: Standard Read Protocol is used.
1: Early Read Protocol is used.
• ACSS: Address to Chip Select Setup
ACSS
0
0
0
1
1
0
1
1
Chip Select Waveform
Standard, asserted at the beginning of the access and deasserted at the end.
One cycle less at the beginning and the end of the access.
Two cycles less at the beginning and the end of the access.
Three cycles less at the beginning and the end of the access.
• RWSETUP: Read and Write Signal Setup Time
See definition and description below.
• RWHOLD: Read and Write Signal Hold Time
See definition and description below.
RWSETUP⁽¹⁾
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
NRD Setup
½ cycle⁽²⁾or
0 cycles⁽³⁾
1 + ½ cycles
2 + ½ cycles
3 + ½ cycles
4 + ½ cycles
5 + ½ cycles
6 + ½ cycles
7 + ½ cycles
NWR Setup
½ cycle
1 + ½ cycles
2 + ½ cycles
3 + ½ cycles
4 + ½ cycles
5 + ½ cycles
6 + ½ cycles
7 + ½ cycles
RWHOLD^{(1) (4)}
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
NRD Hold
0
1 cycles
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
NWR Hold
½ cycle
1 cycle
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
Notes:
1. For a visual description, please refer to “Setup and Hold Cycles” on page 174 and the diagrams in Figure 22-45 and Figure
22-46 and Figure 22-47 on page 198.
2. In Standard Read Protocol.
3. In Early Read Protocol. (It is not possible to use the parameters RWSETUP or RWHOLD in this mode.)
4. When the ECC Controller is used, RWHOLD must be programmed to 1 at least.
6222H–ATARM–25-Jan-12
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