AT32UC3A0512_1 Datasheet, PDF (320/826 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

AT32UC3A
26.7.4.2 Parity
The USART supports five parity modes selected by programming the PAR field in the Mode
Register (MR). The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page
321. Even and odd parity bit generation and error detection are supported.
If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a num-
ber of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the
receiver parity checker counts the number of received 1s and reports a parity error if the sam-
pled parity bit does not correspond. If odd parity is selected, the parity generator of the
transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if
the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received
1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is
used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The
receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is
used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The
receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the
transmitter does not generate any parity bit and the receiver does not report any parity error.
Table 26-6 on page 320 shows an example of the parity bit for the character 0x41 (character
ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is
added when a parity is odd, or 0 is added when a parity is even.
Table 26-6. Parity Bit Examples
Character
Hexa
A
0x41
A
0x41
A
0x41
A
0x41
A
0x41
Binary
0100 0001
0100 0001
0100 0001
0100 0001
0100 0001
Parity Bit
1
0
1
0
None
Parity Mode
Odd
Even
Mark
Space
None
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status
Register (CSR). The PARE bit can be cleared by writing the Control Register (CR) with the RST-
STA bit at 1. Figure 26-22 on page 321 illustrates the parity bit status setting and clearing.
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