AT32UC3A0512_1 Datasheet, PDF (173/826 Pages) ATMEL Corporation – AVR32 32-Bit Microcontroller

Figure 22-2. Output line timings
clock
Write GPIO_OVR to 1
Write GPIO_OVR to 0
GPIO_OVR / I/O Line
GPIO_PVR
PBA Access
AT32UC3A
PBA Access
22.4.7 Interrupts
The GPIO can be programmed to generate an interrupt when it detects an input change on an
I/O line. The module can be configured to signal an interrupt whenever a pin changes value or
only to trigger on rising edges or falling edges. Interrupt is enabled on a pin by setting the corre-
sponding bit in IER (Interrupt Enable Register). The interrupt mode is set by accessing IMR0
(Interrupt Mode Register 0) and IMR1 (Interrupt Mode Register 1). Interrupt can be enabled on a
pin, regardless of the configuration the I/O line, i.e. controlled by the GPIO or assigned to a
peripheral function.
In every port there are four interrupt lines connected to the interrupt controller. Every eigth inter-
rupts in the port are ored together to form an interrupt line.
When an interrupt event is detected on an I/O line, and the corresponding bit in IER is set, the
GPIO interrupt request line is asserted. A number of interrupt signals are ORed-wired together
to generate a single interrupt signal to the interrupt controller.
IFR (Interrupt Flag Register) can by read by software to determine which pin(s) caused the inter-
rupt. The interrupt flag must be manually cleared by writing to IFR.
GPIO interrupts can only be triggered when the GPIO clock is enabled.
22.4.8
Input Glitch Filter
Optional input glitch filters can be enabled on each I/O line. When the glitch filter is enabled, a
glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with dura-
tion of 2 clock cycles or more is accepted. For pulse durations between 1 clock cycle and 2 clock
cycles, the pulse may or may not be taken into account, depending on the precise timing of its
occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 clock cycles, whereas for
a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces
2 clock cycles latency.
The glitch filters are controlled by the register GFER (Glitch Filter Enable Register). When a bit is
set in GFER, the glitch filter on the corresponding pin is enabled. The glitch filter affects only
interrupt inputs. Inputs to peripherals or the value read through PVR are not affected by the
glitch filters.
22.4.9
Interrupt Timings
The figure below shows the timing for rising edge (or pin-change) interrupts when the glitch filter
is disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In
this example, this is not the case for the first pulse. The second pulse is however sampled on a
rising edge and will trigger an interrupt request.
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