ATMEGA325 Datasheet, PDF (31/347 Pages) ATMEL Corporation – 8-bit Microcontroller with In-System Programmable Flash

ATmega325/3250/645/6450
The Oscillator is optimized for use with a 32.768 kHz watch crystal. See Figure 13 on
page 27 for crystal connection.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Reg-
ister is written to logic one. See “Asynchronous operation of the Timer/Counter” on page
138 for further description on selecting external clock as input instead of a 32 kHz
crystal.
System Clock Prescaler
Clock Prescale Register –
CLKPR
The ATmega325/3250/645/6450 system clock can be divided by setting the Clock Pres-
cale Register – CLKPR. This feature can be used to decrease power consumption when
the requirement for processing power is low. This can be used with all clock source
options, and it will affect the clock frequency of the CPU and all synchronous peripher-
als. clk_I/O, clk_ADC, clk_CPU, and clk_FLASH are divided by a factor as shown in Table 13.
Bit
7
6
5
4
3
2
1
0
CLKPCE
–
–
–
CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR
Read/Write
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The
CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to
zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits
are written. Rewriting the CLKPCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKPCE bit.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal
system clock. These bits can be written run-time to vary the clock frequency to suit the
application requirements. As the divider divides the master clock input to the MCU, the
speed of all synchronous peripherals is reduced when a division factor is used. The divi-
sion factors are given in Table 13.
To avoid unintentional changes of clock frequency, a special write procedure must be
followed to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits
in CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to
CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write pro-
cedure is not interrupted.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unpro-
grammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits
are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if
the selected clock source has a higher frequency than the maximum frequency of the
device at the present operating conditions. Note that any value can be written to the
CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must
ensure that a sufficient division factor is chosen if the selected clock source has a higher
frequency than the maximum frequency of the device at the present operating condi-
tions. The device is shipped with the CKDIV8 Fuse programmed.
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2570A–AVR–09/04