ATMEGA325 Datasheet, PDF (168/347 Pages) ATMEL Corporation – 8-bit Microcontroller with In-System Programmable Flash

Multi-processor
Communication Mode
Using MPCMn
Setting the Multi-processor Communication mode (MPCMn) bit in UCSRnA enables a
filtering function of incoming frames received by the USART Receiver. Frames that do
not contain address information will be ignored and not put into the receive buffer. This
effectively reduces the number of incoming frames that has to be handled by the CPU,
in a system with multiple MCUs that communicate via the same serial bus. The Trans-
mitter is unaffected by the MPCMn setting, but has to be used differently when it is a
part of a system utilizing the Multi-processor Communication mode.
If the Receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop
bit indicates if the frame contains data or address information. If the Receiver is set up
for frames with nine data bits, then the ninth bit (RXB8n) is used for identifying address
and data frames. When the frame type bit (the first stop or the ninth bit) is one, the frame
contains an address. When the frame type bit is zero the frame is a data frame.
The Multi-processor Communication mode enables several slave MCUs to receive data
from a master MCU. This is done by first decoding an address frame to find out which
MCU has been addressed. If a particular slave MCU has been addressed, it will receive
the following data frames as normal, while the other slave MCUs will ignore the received
frames until another address frame is received.
For an MCU to act as a master MCU, it can use a 9-bit character frame format (UCSZ =
7). The ninth bit (TXB8n) must be set when an address frame (TXB8n = 1) or cleared
when a data frame (TXB = 0) is being transmitted. The slave MCUs must in this case be
set to use a 9-bit character frame format.
The following procedure should be used to exchange data in Multi-processor Communi-
cation mode:
1. All Slave MCUs are in Multi-processor Communication mode (MPCMn in UCS-
RnA is set).
2. The Master MCU sends an address frame, and all slaves receive and read this
frame. In the Slave MCUs, the RXCn Flag in UCSRnA will be set as normal.
3. Each Slave MCU reads the UDRn Register and determines if it has been
selected. If so, it clears the MPCMn bit in UCSRnA, otherwise it waits for the next
address byte and keeps the MPCMn setting.
4. The addressed MCU will receive all data frames until a new address frame is
received. The other Slave MCUs, which still have the MPCMn bit set, will ignore
the data frames.
5. When the last data frame is received by the addressed MCU, the addressed
MCU sets the MPCMn bit and waits for a new address frame from master. The
process then repeats from 2.
Using any of the 5- to 8-bit character frame formats is possible, but impractical since the
Receiver must change between using n and n+1 character frame formats. This makes
full-duplex operation difficult since the Transmitter and Receiver uses the same charac-
ter size setting. If 5- to 8-bit character frames are used, the Transmitter must be set to
use two stop bit (USBSn = 1) since the first stop bit is used for indicating the frame type.
Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit.
The MPCMn bit shares the same I/O location as the TXCn Flag and this might acciden-
tally be cleared when using SBI or CBI instructions.
168 ATmega325/3250/645/6450
2570A–AVR–09/04