ATMEGA325 Datasheet, PDF (186/347 Pages) ATMEL Corporation – 8-bit Microcontroller with In-System Programmable Flash

Read/Write
Initial Value
USISIE
R/W
0
USIOIE
R/W
0
USIWM1
R/W
0
USIWM0
R/W
0
USICS1
R/W
0
USICS0
R/W
0
USICLK
W
0
USITC
W
0
USICR
The Control Register includes interrupt enable control, wire mode setting, Clock Select
setting, and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending
interrupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will
immediately be executed. Refer to the USISIF bit description on page 185 for further
details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending inter-
rupt when the USIOIE and the Global Interrupt Enable Flag is set to one, this will
immediately be executed. Refer to the USIOIF bit description on page 185 for further
details.
• Bit 5..4 – USIWM1..0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the out-
puts are affected by these bits. Data and clock inputs are not affected by the mode
selected and will always have the same function. The counter and Shift Register can
therefore be clocked externally, and data input sampled, even when outputs are dis-
abled. The relations between USIWM1..0 and the USI operation is summarized in Table
81.
186 ATmega325/3250/645/6450
2570A–AVR–09/04