U5020M Datasheet, PDF (3/10 Pages) TEMIC Semiconductors – Digital Window Watchdog Timer

U5020M
Pin Description
Pin
Symbol
1
TM
2
TM
3 to 8
WAKE-UP
9
ENA
10
RESET
11
TRIG
12
MODE
13
VDD
14
GND
15
OSC
16
TS
Function
Test must not be connected
Test must be connected to GND
Wake-up inputs (pull-down resistor)
There are six digitally debounced wake-up inputs. During the long trigger mode each signal slope at the
inputs initiates a reset pulse at pin 10.
Enable output (push-pull)
It is used for the control of peripheral components. It is activated after the processor triggers three times
correctly.
Reset output (open drain)
Resets the processor in the case of a trigger error or if a wake-up pulse occurs during the long watchdog
period.
Trigger input (pull-up resistor)
It is connected to the microprocessor’s trigger signal.
Mode input (pull-up resistor)
The processor’s mode signal initiates the switchover between the long and the short watchdog time.
Supply voltage
Ground, reference voltage
RC oscillator
Time switch input
Programming pin to select different time durations for the long watchdog time.
Functional
Description
Supply, Pin 13
RC Oscillator, Pin 15
The U5020M requires a stabilized supply voltage V_DD = 5 V ±5% to comply with its elec-
trical characteristics.
An external buffer capacitor of C = 10 nF may be connected between pin 13 and GND.
The clock frequency, f, can be adjusted by the components R₁ and C₁ according to the
formula:
f = ¹--
t
where t = 1.35 + 1.57 R₁ (C₁ + 0.01)
R₁ in kW, C₁ in nF and t in µs
The clock frequency determines all time periods of the logic part as shown in the table
“Electrical Characteristics” under the subheading “Timing” on page 8. With an appropri-
ate component selection, the clock frequency, f, is nearly independent of the supply
voltage as shown in Figure 3 on page 4.
Frequency tolerance Df_max = 10% with R₁ ±1%, C1 = ±5%
3
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