AT90CAN128-15AZ Datasheet, PDF (249/431 Pages) ATMEL Corporation – 8-bit Microcontroller with 32K/64K/128K Bytes of ISP Flash and CAN Controller

AT90CAN32/64/128
Figure 19-14. CAN Controller Interrupt Structure
CANSTMOB.6
CANSTMOB.5
CANSTMOB.4
CANSTMOB.3
CANSTMOB.2
CANSTMOB.1
CANSTMOB.0
CANGIE.4
ENTX
CANGIE.5
ENRX
CANGIE.3
ENERR
TXOK[i]
RXOK[i]
BERR[i]
SERR[i]
CANSIT 1/2
SIT[i]
CANIE 1/2
IEMOB[i]
i=0
CERR[i]
FERR[i]
AERR[i]
i=14
CANGIE.2
ENBX
CANGIE.1
ENERG
CANGIE.6
ENBOFF
CANGIT.7
CANIT
CANGIE.7
ENIT
CANGIT.4 BXOK
CAN IT
CANGIT.3 SERG
CANGIT.2 CERG
CANGIT.1 FERG
CANGIT.0 AERG
CANGIT.6 BOFFI
CANGIE.0
ENOVRT
CANGIT.5 OVRTIM
OVR IT
19.8.2
Interrupt Behavior
When an interrupt occurs, an interrupt flag bit is set in the corresponding MOb-CANSTMOB reg-
ister or in the general CANGIT register. If in the CANIE register, ENRX / ENTX / ENERR bit are
set, then the corresponding MOb bit is set in the CANSITn register.
To acknowledge a MOb interrupt, the corresponding bits of CANSTMOB register (RXOK,
TXOK,...) must be cleared by the software application. This operation needs a read-modify-write
software routine.
To acknowledge a general interrupt, the corresponding bits of CANGIT register (BXOK, BOF-
FIT,...) must be cleared by the software application. This operation is made writing a logical one
in these interrupt flags (writing a logical zero doesn’t change the interrupt flag value).
OVRTIM interrupt flag is reset as the other interrupt sources of CANGIT register and is also
reset entering in its dedicated interrupt handler.
When the CAN node is in transmission and detects a Form Error in its frame, a bit Error will also
be raised. Consequently, two consecutive interrupts can occur, both due to the same error.
When a MOb error occurs and is set in its own CANSTMOB register, no general error is set in
CANGIT register.
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