AT90CAN128-15AZ Datasheet, PDF (134/431 Pages) ATMEL Corporation – 8-bit Microcontroller with 32K/64K/128K Bytes of ISP Flash and CAN Controller

The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCRnx is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
13.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clk_Tn) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCRnx Register is updated with the OCRnx buffer value (only for
modes utilizing double buffering). Figure 13-10 shows a timing diagram for the setting of OCFnx.
Figure 13-10. Timer/Counter Timing Diagram, Setting of OCFnx, no Prescaling
clk_I/O
clk_Tn
(cl_Ik_/O/1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 13-11 shows the same timing data, but with the prescaler enabled.
Figure 13-11. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f_{clk_I/O}/8)
clk_I/O
clk_Tn
(cl_Ik_/O/8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 13-12 shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCRnx Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOVn flag at BOTTOM.
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