AT90CAN128-15AZ Datasheet, PDF (111/431 Pages) ATMEL Corporation – 8-bit Microcontroller with 32K/64K/128K Bytes of ISP Flash and CAN Controller

AT90CAN32/64/128
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page 105
for more details.
Table 12-4 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase cor-
rect PWM mode.
Table 12-4.
COM0A1
0
0
1
1
Compare Output Mode, Phase Correct PWM Mode⁽¹⁾
COM0A0 Description
0
Normal port operation, OC0A disconnected.
1
Reserved
0
Clear OC0A on compare match when up-counting.
Set OC0A on compare match when downcounting.
Set OC0A on compare match when up-counting.
1
Clear OC0A on compare match when downcounting.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the com-
pare match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode” on
page 107 for more details.
• Bit 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 12-5. Clock Select Bit Description
CS02 CS01 CS00 Description
0
0
0
No clock source (Timer/Counter stopped)
0
0
1
clk_I/O/(No prescaling)
0
1
0
clk_I/O/8 (From prescaler)
0
1
1
clk_I/O/64 (From prescaler)
1
0
0
clk_I/O/256 (From prescaler)
1
0
1
clk_I/O/1024 (From prescaler)
1
1
0
External clock source on T0 pin. Clock on falling edge.
1
1
1
External clock source on T0 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
12.9.2
Timer/Counter0 Register – TCNT0
Bit
Read/Write
Initial Value
7
6
5
4
3
2
1
0
TCNT0[7:0]
TCNT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the compare
match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a compare match between TCNT0 and the OCR0A Register.
7682C–AUTO–04/08
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