ATMEGA3290P_14 Datasheet, PDF (235/427 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega329P/3290P
23.3.5
Figure 23-6. Driving a LCD with Four Common Terminals
V_LCD
2_/3VLCD
1_/3VLCD
GND
SEG0
V_LCD
2_/3VLCD
1_/3VLCD
GND
SEG0
V_LCD
2_/3VLCD
1_/3VLCD
GND
COM0
V_LCD
2_/3VLCD
1_/3VLCD
GND
COM1
V_LCD
2_/3VLCD
1_/3VLCD
GND
-¹/₃V_LCD
-²/₃V_LCD
-V_LCD
Low Power Waveform
Frame
Frame
SEG0 - COM0
V_LCD
2_/3VLCD
1_/3VLCD
GND
-¹/₃V_LCD
-²/₃V_LCD
-V_LCD
Frame
SEG0 - COM1
Frame
To reduce toggle activity and hence power consumption a low power waveform can be selected
by writing LCDAB to one. Low power waveform requires two subsequent frames with the same
display data to obtain zero DC voltage. Consequently data latching and Interrupt Flag is only set
every second frame. Default and low power waveform is shown in Figure 23-7 for 1/3 duty and
1/3 bias. For other selections of duty and bias, the effect is similar.
Figure 23-7. Default and Low Power Waveform
23.3.6
V_LCD
2_/3VLCD
1_/3VLCD
GND
SEG0
V_LCD
2_/3VLCD
1_/3VLCD
GND
SEG0
V_LCD
2_/3VLCD
1_/3VLCD
GND
COM0
V_LCD
2_/3VLCD
1_/3VLCD
GND
COM0
V_LCD
2_/3VLCD
1_/3VLCD
GND
-¹/₃V_LCD
-²/₃V_LCD
-V_LCD
Operation in Sleep Mode
Frame
Frame
SEG0 - COM0
V_LCD
2_/3VLCD
1_/3VLCD
GND
-¹/₃V_LCD
-²/₃V_LCD
-V_LCD
Frame
SEG0 - COM0
Frame
When synchronous LCD clock is selected (LCDCS = 0) the LCD display will operate in Idle
mode and Power-save mode with any clock source.
An asynchronous clock from TOSC1 can be selected as LCD clock by writing the LCDCS bit to
one when Calibrated Internal RC Oscillator is selected as system clock source. The LCD will
then operate in Idle mode, ADC Noise Reduction mode and Power-save mode.
When EXCLK in ASSR Register is written to one, and asynchronous clock is selected, the exter-
nal clock input buffer is enabled and an external clock can be input on Timer Oscillator 1
8021G–AVR–03/11
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