ATMEGA3290P_14 Datasheet, PDF (171/427 Pages) ATMEL Corporation – High Endurance Non-volatile Memory segments

ATmega329P/3290P
Figure 19-1. USART Block Diagram⁽¹⁾
UBRR[H:L]
BAUD RATE GENERATOR
UDR (Transmit)
TRANSMIT SHIFT REGISTER
RECEIVE SHIFT REGISTER
UDR (Receive)
Clock Generator
OSC
SYNC LOGIC
PARITY
GENERATOR
CLOCK
RECOVERY
DATA
RECOVERY
PARITY
CHECKER
PIN
CONTROL
XCK
Transmitter
TX
CONTROL
PIN
CONTROL
TxD
Receiver
RX
CONTROL
PIN
CONTROL
RxD
UCSRA
UCSRB
UCSRC
Note: 1. Refer to Figure 1-2 on page 3, Figure on page 3, and ”Alternate Functions of Port E” on page
78 for USART pin placement.
The dashed boxes in the block diagram separate the three main parts of the USART (listed from
the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units.
The Clock Generation logic consists of synchronization logic for external clock input used by
synchronous slave operation, and the baud rate generator. The XCK (Transfer Clock) pin is only
used by synchronous transfer mode. The Transmitter consists of a single write buffer, a serial
Shift Register, Parity Generator and Control logic for handling different serial frame formats. The
write buffer allows a continuous transfer of data without any delay between frames. The
Receiver is the most complex part of the USART module due to its clock and data recovery
units. The recovery units are used for asynchronous data reception. In addition to the recovery
units, the Receiver includes a Parity Checker, Control logic, a Shift Register and a two level
receive buffer (UDRn). The Receiver supports the same frame formats as the Transmitter, and
can detect Frame Error, Data OverRun and Parity Errors.
8021G–AVR–03/11
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