ATMEGA16M1_1 Datasheet, PDF (235/365 Pages) ATMEL Corporation – 8-bit Microcontroller with 16K/32K/64K Bytes In-System Programmable Flash

ATmega16/32/64/M1/C1
Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Next Conversion
Cycle Number
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
ADCL
Prescaler
Reset
1
2
3
4
5
6
7
8
MUX and REFS
Update
Sample &
Hold
11 12 13 14
1
2
Conversion
Complete
Sign and MSB of Result
LSB of Result
Prescaler
Reset
Figure 18-7. ADC Timing Diagram, Free Running Conversion
One Conversion
Next Conversion
Cycle Number ^{12 13 14 1}
2
3
4
5
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Conversion
Complete
Sample & Hold
MUX and REFS
Update
Table 18-1. ADC Conversion Time
Condition
Sample & Hold
(Cycles from Start of Conversion)
Conversion Time
(Cycles)
First Conversion
13.5
25
Normal
Conversion,
Single Ended
3.5
15.5
Auto Triggered
Conversion
2
16
18.5
Changing Channel or Reference Selection
The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a temporary
register to which the CPU has random access. This ensures that the channels and reference
selection only takes place at a safe point during the conversion. The channel and reference
selection is continuously updated until a conversion is started. Once the conversion starts, the
channel and reference selection is locked to ensure a sufficient sampling time for the ADC. Con-
tinuous updating resumes in the last eight ADC clock cycle before the conversion completes
(ADIF in ADCSRA is set). Note that the conversion starts on the second following rising CPU
clock edge after ADSC is written. The user is thus advised not to write new channel or reference
selection values to ADMUX until two ADC clock cycle after ADSC is written.
7647F–AVR–04/09
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