ATMEGA16M1_1 Datasheet, PDF (220/365 Pages) ATMEL Corporation – 8-bit Microcontroller with 16K/32K/64K Bytes In-System Programmable Flash

17.5.11
Break-in-data
According to the LIN protocol, the LIN/UART controller can detect the BREAK/SYNC field
sequence even if the break is partially superimposed with a byte of the response. When a
BREAK/SYNC field sequence happens, the transfer in progress is aborted and the processing of
the new frame starts.
• On slave node(s), an error is generated (i.e. LBERR in case of Tx Response or LFERR in
case of Rx Response). Information on data error is also available, refer to the Section
17.5.7.5.
• On master node, the user (code) is responsible for this aborting of frame. To do this, the
master task has first to abort the on-going communication (clearing LCMD bits - LIN Abort
command) and then to apply the Tx Header command. In this case, the abort error flag -
LABORT - is set.
On the slave node, the BREAK detection is processed with the synchronization setting available
when the LIN/UART controller processed the (aborted) response. But the re-synchronization
restarts as usual. Due to a possible difference of timing reference between the BREAK field and
the rest of the frame, the time-out values can be slightly inaccurate.
17.5.12 Checksum
The last field of a frame is the checksum.
In LIN 2.1, the checksum contains the inverted eight bit sum with carry over all data bytes and
the protected identifier. This calculation is called enhanced checksum.
⎛
⎛⎛ⁿ
⎞
⎞
⎛⎛⎛ⁿ
⎞
⎞ ⎞⎞
∑ ∑ ^CHECKSUM
=
255
–
⎜⎜ ^unsigned
char _⎜⎜
⎜
⎜
DATA
⎟
n⎟
+
PROTECTED
ID._⎟⎟
+
unsigned
char _{⎜⎜ ⎜⎜}
⎜
⎜
DATA
⎟
n⎟
+
PROTECTED
ID._⎟⎟
»
8_{⎟⎟ ⎟⎟}
⎝
⎝⎝₀
⎠
⎠
⎝⎝⎝₀
⎠
⎠ ⎠⎠
In LIN 1.3, the checksum contains the inverted eight bit sum with carry over all data bytes. This
calculation is called classic checksum.
⎛
⎛ⁿ
⎞
⎛⎛ⁿ
⎞ ⎞⎞
∑ ∑ ^{CHECKSUM = 255 –} _⎜⎜^{unsigned char}_⎜⎜
DATA
⎟
n⎟
+
unsigned
char
⎜⎜
⎜⎜
DATA
⎟
n⎟
»
8_{⎟⎟⎟⎟}
⎝
⎝₀
⎠
⎝⎝₀
⎠ ⎠⎠
Frame identifiers 60 (0x3C) to 61 (0x3D) shall always use classic checksum
17.5.13 Interrupts
As shown in Figure 17-13 on page 221, the four communication flags of the LINSIR register are
combined to drive two interrupts. Each of these flags have their respective enable interrupt bit in
LINENIR register.
(see Section 17.5.8 “xxOK Flags” on page 218 and Section 17.5.9 “xxERR Flags” on page 218).
220 ATmega16/32/64/M1/C1
7647F–AVR–04/09