ATTINY48PRE Datasheet, PDF (22/298 Pages) ATMEL Corporation – 123 Powerful Instructions – Most Single Clock Cycle Execution

5.5 Register Description
5.5.1
EEARH and EEARL – EEPROM Address Register
Bit
15
14
13
–
–
–
0x21 (0x41)
–
–
EEAR5
7
6
5
Read/Write
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
X
12
–
EEAR4
4
R
R/W
0
X
11
–
EEAR3
3
R
R/W
0
X
10
–
EEAR2
2
R
R/W
0
X
9
–
EEAR1
1
R
R/W
0
X
8
–
EEAR0
0
R
R/W
0
X
EEARH
EEARL
• Bits 15:6 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 5:0 – EEAR[5:0]: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
64/64 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
63/63. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
5.5.2 EEDR – EEPROM Data Register
Bit
0x20 (0x40)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
MSB
LSB
EEDR
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
• Bits 7:0 – EEDR[7:0]: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
5.5.3
EECR – EEPROM Control Register
Bit
7
6
0x1F (0x3F)
–
–
Read/Write
R
R
Initial Value
0
0
5
EEPM1
R/W
X
4
EEPM0
R/W
X
3
EERIE
R/W
0
2
EEMPE
R/W
0
1
EEPE
R/W
X
0
EERE
R/W
0
EECR
• Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 5:4 – EEPM[1:0]: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be trig-
gered when writing EEPE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in Table 5-1. While EEPE
22 ATtiny48/88
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