ATTINY48PRE Datasheet, PDF (112/298 Pages) ATMEL Corporation – 123 Powerful Instructions – Most Single Clock Cycle Execution

Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
12.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A
Bit
(0x89)
(0x88)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR1A[15:8]
OCR1AH
OCR1A[7:0]
OCR1AL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
12.11.6
OCR1BH and OCR1BL – Output Compare Register 1 B
Bit
(0x8B)
(0x8A)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
OCR1B[15:8]
OCR1BH
OCR1B[7:0]
OCR1BL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See “Accessing 16-bit Registers” on page 89.
12.11.7
ICR1H and ICR1L – Input Capture Register 1
Bit
(0x87)
(0x86)
Read/Write
Initial Value
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 89.
12.11.8 TIMSK1 – Timer/Counter1 Interrupt Mask Register
Bit
7
6
5
4
(0x6F)
–
–
ICIE1
–
Read/Write
R
R
R/W
R
Initial Value
0
0
0
0
3
2
1
0
–
OCIE1B OCIE1A TOIE1
TIMSK1
R
R/W
R/W
R/W
0
0
0
0
• Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read zero.
112 ATtiny48/88
8008F–AVR–06/10