ATTINY48PRE Datasheet, PDF(102/298 Page) ATMEL Corporation – 123 Powerful Instructions – Most Single Clock Cycle Execution

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ATTINY48PRE Datasheet, PDF (102/298 Pages) ATMEL Corporation – 123 Powerful Instructions – Most Single Clock Cycle Execution

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inverted. The dual-slope operation has lower maximum operation frequency than single slope

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes

are preferred for motor control applications.

The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined

by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to

0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolu-

tion in bits can be calculated by using the following equation:

RPCPWM = l--o---g----(-l-o-T--g-O---(--P-2---)-+-----1----)

In phase correct PWM mode the counter is incremented until the counter value matches either

one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM1[3:0] = 1, 2, or 3), the value in ICR1

(WGM1[3:0] = 10), or the value in OCR1A (WGM1[3:0] = 11). The counter has then reached the

TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock

cycle. The timing diagram for the phase correct PWM mode is shown on Figure 12-8. The figure

shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1

value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The

diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on

the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Inter-

rupt Flag will be set when a compare match occurs.

Figure 12-8. Phase Correct PWM Mode, Timing Diagram

OCRnx/TOPUpdate and

OCnA Interrupt Flag Set

or ICFn Interrupt Flag Set

(Interrupt on TOP)

TOVn Interrupt Flag Set

(Interrupt on Bottom)

TCNTn

OCnx

OCnx

(COMnx[1:0] = 2)

(COMnx[1:0] = 3)

Period

1

2

3

4

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When

either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord-

ingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer

value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter

reaches the TOP or BOTTOM value.

102 ATtiny48/88

8008FâAVRâ06/10

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