ATMEGA649 Datasheet, PDF (204/375 Pages) ATMEL Corporation – 8-bit Microcontroller with In-System Programmable Flash

Figure 84. Analog to Digital Converter Block Schematic
ADC CONVERSION
COMPLETE IRQ
8-BIT DATA BUS
ADC MULTIPLEXER
SELECT (ADMUX)
INTERRUPT
FLAGS
ADTS[2:0]
ADC CTRL. & STATUS
REGISTER (ADCSRA)
15
0
ADC DATA REGISTER
(ADCH/ADCL)
MUX DECODER
TRIGGER
SELECT
PRESCALER
START
AVCC
AREF
INTERNAL
REFERENCE
GND
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
BANDGAP
REFERENCE
POS.
INPUT
MUX
CONVERSION LOGIC
10-BIT DAC
SAMPLE & HOLD
COMPARATOR
-
+
SINGLE ENDED / DIFFERENTIAL SELECTION
DIFFERENTIAL
AMPLIFIER
+
-
ADC MULTIPLEXER
OUTPUT
NEG.
INPUT
MUX
Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive
approximation. The minimum value represents GND and the maximum value represents
the voltage on the AREF pin minus 1 LSB. Optionally, AVCC or an internal 1.1V refer-
ence voltage may be connected to the AREF pin by writing to the REFSn bits in the
ADMUX Register. The internal voltage reference may thus be decoupled by an external
capacitor at the AREF pin to improve noise immunity.
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the
ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected
as single ended inputs to the ADC. The ADC is enabled by setting the ADC Enable bit,
ADEN in ADCSRA. Voltage reference and input channel selections will not go into effect
until ADEN is set. The ADC does not consume power when ADEN is cleared, so it is
recommended to switch off the ADC before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers,
ADCH and ADCL. By default, the result is presented right adjusted, but can optionally
be presented left adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to
read ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content
of the Data Registers belongs to the same conversion. Once ADCL is read, ADC access
204 ATmega329/3290/649/6490
2552H–AVR–11/06