ATMEGA88PA_14 Datasheet, PDF (174/326 Pages) ATMEL Corporation – ATMEL 8-BIT MICROCONTROLLER

Table 20-11. UCSZn Bits Settings
UCSZn2
UCSZn1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
UCSZn0
0
1
0
1
0
1
0
1
Character Size
5-bit
6-bit
7-bit
8-bit
Reserved
Reserved
Reserved
9-bit
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is used. The UCPOLn bit sets
the relationship between data output change and data input sample, and the synchronous clock (XCKn).
Table 20-12. UCPOLn Bit Settings
UCPOLn Transmitted Data Changed (Output of TxDn Pin) Received Data Sampled (Input on RxDn Pin)
0
Rising XCKn edge
Falling XCKn edge
1
Falling XCKn edge
Rising XCKn edge
20.11.5 UBRRnL and UBRRnH – USART Baud Rate Registers
Bit
15
14
13
12
11
10
9
8
–
–
–
–
UBRRn[11:8]
UBRRnH
UBRRn[7:0]
UBRRnL
7
6
5
4
3
2
1
0
R
R
R
R
R/W
R/W
R/W
R/W
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Initial Value
0
0
0
0
0
0
0
0
• Bit 15:12 – Reserved
These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRnH
is written.
• Bit 11:0 – UBRR[11:0]: USART Baud Rate Register
This is a 12-bit register which contains the USART baud rate. The UBRRnH contains the four most significant bits, and the
UBRRnL contains the eight least significant bits of the USART baud rate. Ongoing transmissions by the Transmitter and
Receiver will be corrupted if the baud rate is changed. Writing UBRRnL will trigger an immediate update of the baud rate
prescaler.
174 ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14