AT89C5131A-M_14 Datasheet, PDF (169/188 Pages) ATMEL Corporation – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode

AT89C5130A/31A-M
27.4.6 External Data Memory Read Cycle
ALE
T_LLDV
T_WHLH
PSEN
RD
PORT 0
PORT 2
ADDRESS
OR SFR-P2
T_LLWL
T_RLRH
T_LLAX
A0-A7
T_AVWL
T_AVDV
T_RLAZ
T_RHDX
DATA IN
ADDRESS A8-A15 OR SFR P2
T_RHDZ
27.4.7
Serial Port Timing - Shift Register Mode
Table 27-8. Symbol Description (F = 40 MHz)
Symbol
T_XLXL
T_QVHX
T_XHQX
T_XHDX
T_XHDV
Parameter
Serial port clock cycle time
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Table 27-9. AC Parameters for a Fix Clock (F = 40 MHz)
Symbol
Min
Max
T_XLXL
T_QVHX
T_XHQX
T_XHDX
T_XHDV
300
200
30
0
117
Units
ns
ns
ns
ns
ns
Table 27-10. AC Parameters for a Variable Clock
Symbol
T_XLXL
T_QVHX
T_XHQX
T_XHDX
T_XHDV
Type
Min
Min
Min
Min
Max
Standard
Clock
12 T
10 T - x
2T-x
x
10 T - x
X2 Clock
6T
5T-x
T-x
x
5 T- x
X Parameter
for -M Range
50
20
0
133
Units
ns
ns
ns
ns
ns
4337K–USB–04/08
169