AT91C140_05 Datasheet, PDF (150/174 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

the clock signal on which the data are driven and sampled. Each of the two parameters has
two possible states, resulting in four possible combinations that are incompatible with one
another. Thus a master/slave pair must use the same parameter pair values to communicate.
If multiple slaves are used and fixed in different configurations, the master must reconfigure
itself each time it needs to communicate with a different slave.
Table 21-2 shows the four modes and corresponding parameter settings.
Table 21-2.
SPI Bus Protocol Mode
SPI Mode
0
1
2
3
CPOL
0
0
1
1
CPHA
0
1
0
1
Figure 21-6 and Figure 21-7 show examples of data transfers.
Figure 21-6. SPI Transfer Format (NCPHA = 1, 8 bits per transfer
SPCK cycle (for reference)
1
2
3
4
5
6
7
8
SPCK
(CPOL=0)
SPCK
(CPOL=1)
MOSI
(from master)
MSB
6
5
4
3
2
1
LSB
MISO
(from slave)
MSB
6
5
4
3
2
1
LSB
*
NSS (to slave)
* Not defined, but normally MSB of previous character received.
150 AT91C140
6069C–ATARM–15-Sep-05