AT91C140_05 Datasheet, PDF (100/174 Pages) ATMEL Corporation – AT91 ARM Thumb Microcontrollers

19.4.1
Receiver Ready
When a complete character is received, it is transferred to the US_RHR and the RXRDY sta-
tus bit in US_CSR is set. If US_RHR has not been read since the last transfer, the OVRE
status bit in US_CSR is set.
19.4.2 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits in
accordance with the field PAR in US_MR. It then compares the result with the received parity
bit. If different, the parity error bit PARE in US_CSR is set.
19.4.3
Framing Error
If a character is received with a stop bit at low level and with at least one data bit at high level,
a framing error is generated. This sets FRAME in US_CSR.
19.4.4 Time-out
This function allows an idle condition on the RXD line to be detected. The maximum delay for
which the UART should wait for a new character to arrive while the RXD line is inactive (high
level) is programmed in US_RTOR. When this register is set to 0, no time-out is detected. Oth-
erwise, the receiver waits for a first character and then initializes a counter which is
decremented at each bit period and reloaded at each byte reception. When the counter
reaches 0, the TIMEOUT bit in US_CSR is set. The user can restart the wait for a first charac-
ter with the STTTO (Start Time-out) bit in US_CR.
Calculation of time-out duration:
Duration = Value × 4 × Bit Period
19.5 Transmitter
Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first, on the
falling edge of the serial clock.
The number of data bits is selected in the CHRL field in US_MR.
The parity bit is set according to the PAR field in US_MR.
The number of stop bits is selected in the NBSTOP field in US_MR.
When a character is written to US_THR, it is transferred to the Shift Register as soon as it is
empty. When the transfer occurs, the TXRDY bit in US_CSR is set until a new character is
written to US_THR. If the Transmit Shift Register and US_THR are both empty, the TXEMPTY
bit in US_CSR is set.
Figure 19-5. Character Transmission
Example: 8-bit, parity enabled 1 stop
Baud Rate
Clock
TXD
Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop
Bit
Bit Bit
100 AT91C140
6069C–ATARM–15-Sep-05