AT75C Datasheet, PDF (142/171 Pages) ATMEL Corporation – Smart Internet Appliance Processor (SIAP)

INT0, INT1, INT2
Operation
TRAP/BI Operation
INT0, INT1 and INT2 are individually maskable interrupts. A maskable interrupt is
accepted when:
• the OakDSPCore is in an interruptable state (see “Interrupt Latency”)
• the global Interrupt Enable bit within ST0 is set
• the corresponding Interrupt Mask bit (IM0, IM1 or IM2) is set
When a maskable interrupt is accepted, the OakDSPCore performs the following:
• SP - 1 –> SP
The stack pointer is pre-decremented.
• PC –> (SP)
The program counter is saved into the stack.
• ##ISR address –> PC
Control is given to the interrupt service routine.
It should be noted that the IMx mask remains unaffected.
When the interrupt request is acknowledged by the OakDSPCore, the IE bit within ST0
is reset, disabling other maskable interrupts from being serviced. Additional pending
interrupts are serviced once the program re-enables (sets) the IE bit.
Return from the interrupt service routine is down through the instructions ret, retd, reti,
or retid. The instructions reti and retid set the IE flag, allowing pending interrupts to be
serviced. When using the ret or retd instructions, the IE bit must be set explicitly to
enable interrupts again.
Interrupt priority is used to arbitrate simultaneous interrupt requests. INT0 has the high-
est priority, and INT2 the lowest. Nesting is supported if IE is enabled by the current
interrupt service routine. The priority between INT0, INT1 and INT2 is significant only if
more than one interrupt is received at the same time. The priority scheme is also applied
when the IE bit is cleared for some time and more than one maskable interrupt request
is received.
When a maskable interrupt INTx is accepted, the corresponding IPx bit in ST2 is set.
This can be used in applications that use interrupt polling while disabling (via the IE bit)
the automatic response to interrupt requests.
TRAP is a software interrupt used to mimic hardware interrupts, while BI is a hardware
breakpoint interrupt dedicated to the on-chip emulation module (OCEM) operation. Both
TRAP and BI share the same interrupt vector.
During the execution of the TRAP/BI service routine, all other interrupts are disabled.
A TRAP/BI is accepted while the OakDSPCore is in an interruptible state, as stated in
“Interrupt Latency”. When the OakDSPCore accepts the TRAP/BI, the following actions
are taken:
• SP - 1 –> SP
The stack pointer is decremented.
• PC –> (SP)
The program counter is saved into the stack.
• PC –> DVM
The program counter is saved into the Data Value Match register.
• 0x0002 –> PC
Control is given to the TRAP service routine.
142 _{AT75C DSP Subsystem}
1368C–INTAP–08/02