EVLB001 Datasheet, PDF (11/35 Pages) ATMEL Corporation – Automatic microcontroller dimmable ballast

Ballast Demonstrator Operation
The maximum current the PFC MOSFET (Q3) can sustain is 4.5A. The relation between
PW and the peak current in PFC MOSFET (Q3) is:
PW = t = L x Ipk / Vhaversine_max
With L at 700µH and Ipk at 4.5A, PWmax = 8.5µS at high line (265 Vrms).
With L at 700µH and Ipk at 4.5A, PWmax = 24.7µS at high line (90 Vrms).
This also effectively limits the FET dissipation under upset conditions. Under normal
operation, a pulse width maximum of 25µS is allowed for a maximum bus voltage error
with the high line limitation. Regulation of 1% of the VBUS is achieved with this control
scheme.
After the PFC FET ON pulse, the PFC inductor flyback boosts the voltage through the
PFC diode to the bulk filter capacitor. The boost current decays as measured by the
inductor secondary. After the current goes to zero, the next pulse is started. This
ensures operation in a critical conduction boost mode. The current zero crossing detec-
tion of PD7 sets the PFC off time. This off time is effectively proportional to the
haversine amplitude with the lowest PFC frequency occurring at the haversine crest and
the highest frequency at the haversine zero. Because of the haversine voltage and
di=v*dt/L, the mains current envelope should follow the voltage for near unity power fac-
tor. This assumes a nearly constant error (di) of the DC bus over each haversine period.
4.4.1
System Sequential
Step Description
The PFC ON time is modified proportionally to the error between 400V and the actual
value of the bus. In case the Vbus reaches the overshoot value of 415V the pulse is
reduced to 0.
This control loop will determine the regulation response to ripple current on the 400V
bulk filter cap and the loads for a specific application design requirements.
Main voltage applied.
Undervoltage lockout (UVLO) released.
IXI859 voltage regulator supplies 3.3V to microcontroller.
Power microcontroller ON in low current standby mode.
Disable half bridge drive output PB0 & PB1
Disable PD5 comparator (Not implemented).
PB7, scaled haversine voltage must be >0.848 Vmin (90VAC) & <2.497 (265VAC)
Vmax (haversine peak) for the PFC to start.
PD0 soft start PFC with 10µS pulses at 50µS period for 800µS.
Monitor comparator at PD7 for change 1 to 0 indicating a zero crossing of the PFC
inductor secondary voltage. This occurs after the 10µS start pulse burst.
If no PD7 change and after 800µS halt PD0, wait 1 second and provide again PD0 with
10µS pulses for 800µS. Try 10 times and if no crossing, set PFC alarm.
After PD7 comparator transition and 400VDC (2.368V at PB2), enable PFC control loop.
-Adjust PB2 (400VDC sense) setpoint to 2.368V with deadband.
-If PB2 > 2.50V then inhibit PD0 pulse.
-If PB2 = < 2.368V then use the control loop to establish the PD0 PFC pulse width.
4-9
7597B–AVR–10/07
ATAVRFBKIT / EVLB001 User Guide