EVLB001 Datasheet, PDF (10/35 Pages) ATMEL Corporation – Automatic microcontroller dimmable ballast

Ballast Demonstrator Operation
4.3
Circuit Topology Input filter with varistor for noise suppression and protection.
PFC / boost circuit including IXI859 MOSFET driver
AT90PWM2B/216 microcontroller 24 pin SOIC
half bridge driver
half bridge power MOSFET stage for up to 2 lamps
Voltage driven filaments for wider lamp variety and better stability under all conditions
400VDC bus voltage after the PFC boost
4.4 Startup and PFC
Description
Upon application of main power, the microcontroller does not drive the PFC MOSFET
Q3. The C9 capacitor is charged to the peak line voltage.
The depletion FET Q1 and the Zener Diode provide a DC voltage with enough current to
supply the control portion of the ballast.
As soon as the microcontroller requests the ballast to start, the PFC is enabled accord-
ing to the following sequence.
The microcontroller checks that the DC bus voltage is 90% of the haversine peak and
the under voltage lockout (UVLO) requirements are met, then a series of fixed width
soft-start pulses are sent to the PFC MOSFET (Q3) at 10 µS at a 20 kHz rate. At very
low load currents the bus voltage should rise to 400V. If the bus rises to 415 VDC all
PFC pulses stop. As the 400V drops, the zero crossing detector PD7 starts to sense a
zero crossing from the PFC transformer secondary. A 400V DC bus and a zero crossing
event start the PFC control loop.
Checks are made to detect the presence of the rectified power (haversine) and bus volt-
age throughout normal operation. Main supply voltage senses at PB7 < 0.848 (90 VAC)
or > 2.497 (265 VAC) peak faults the PFC to off, turns off the PFC MOSFET (Q3) and
initiates a restart.
Main Supply
Voltage
Ipeak = Vin x Ton / L
Imean = Ipeak/2
Actual switching frequency
is higher than shown
PFC
DRIVING
The control consists of measuring the error between VBUS and 400V (2.39V at PB2) to
determine the PFC drive pulse width (PW). The PW is proportional to the error, and has
to be constant over a complete half period. The update is done each time the haversine
reaches zero.
ATAVRFBKIT / EVLB001 User Guide
4-8
7597B–AVR–10/07