AT91SAM7S128C-AU-999 Datasheet, PDF (108/775 Pages) ATMEL Corporation – ARM-based Flash MCU

Figure 19-4. Code Read Optimization in Thumb Mode for FWS = 3
3 Wait State Cycles
3 Wait State Cycles
Master Clock
3 Wait State Cycles
3 Wait State Cycles
ARM Request (16-bit)
Code Fetch
@Byte 0
Flash Access
Buffer (32 bits)
@2 @4
@6 @8
@10 @12
Bytes 0-3
Bytes 4-7
Bytes 8-11
Bytes 12-15
Bytes 0-3
Bytes 4-7
Bytes 8-11
Data To ARM
0-1 2-3
4-5 6-7
8-9 10-11
12-13
Note: When FWS is equal to 2 or 3, in case of sequential reads, the first access takes FWS cycles, the second access one cycle, the
third access FWS cycles, the fourth access one cycle, etc.
SAM7S Series [DATASHEET]
6175M–ATARM–26-Oct-12
108