IC-LV_16 Datasheet, PDF (12/15 Pages) IC-Haus GmbH – 5-BIT OPTO ENCODER

iC-LV
5-BIT OPTO ENCODER
Rev C1, Page 12/15
The synchronization result is switched straight through
to the output so that a synchronized MSB is available
for each following gear. This allows the track data to be
synchronized with MSBs on the first falling as well as
on the first rising edge.
In synchronization modes iC-LV functions as a 4-bit
shift register, i.e. the synchronization bit is not clocked
out with the track data. Serial data is read in on a falling
edge and output on a rising edge. In SSI Out mode the
MSB is blanked out by a high until the first rising edge
and thus output on this first rising edge, making this
mode SSI compatible.
MSB
LSB
D4 D3 D2D1 D0 DB(0)
GRAY2BIN
4
1
ADD /SUB
binary LSB
&
&
SERIN
binary MSB of
predecessor
SEEN
Analog Test Modes (MODE = 0)
Sensor emulation and comparator switching
threshold test: To test the track evaluation and switch-
ing thresholds a test current is supplied at pin SYNM0
for reference sensor DREF and at SYNM1 for the track
sensors. The current reduction ratio is 1:1000.
Alternatively, testing can be carried out by illumination
as the supplied test currents are added to the photocur-
rents. The track to be measured at SOUT is selected
via a 5-bit shift register. To this end a suitable bit stream
is clocked in via SCLK (clock low active) and SERIN
(level). If more than one track is selected, the compara-
tor output signals are EXORed. The 5-bit shift register
addresses track sensors D4 to D0 via bits 4 to 0. When
measurement commences the shift register should be
filled up with zero.
IDDQ test: This test is initiated by connecting pin NDIR
(default high) to GND.
SOUT
SEEN = '1' : SERIN mounted leading:
If DB(0) = '1' and SERIN = '0'
DB(4:1) + 1
SEEN = '0' : SERIN mounted trailing:
If DB(0) = '0' and SERIN = '1'
DB(4:1) - 1
Figure 3: Synchronization
If inverted Gray codes are used on the code discs a
code inversion can be initiated by connecting NINV to
GND. By connecting NDIR to GND the MSB bit is out-
put inverted to reverse the count direction of the Gray
code. Here it should be noted that inverting the MSB
output causes a 180° change in the phase position, i.e.
a trailing 90° synchronization track becomes a leading
90° track and vice versa. This can be compensated for
by a suitable setting of pin SEEN or by assembling the
code disc in a suitable zero position.
Test Modes
Digital Test Modes (MODE = 1, open)
Logic test: Digital test mode is largely identical to the
serial operating modes. One difference is that data
input at pin SERIN is first clocked through a 5-bit shift
register before being clocked through the output shift
register. This enables various bit sequences to be first
clocked into the test register. Following an idle time on
the clock line of t > tmf (see Electrical Characteristics
No. 603) the test data is stored on the first falling edge
on SCLK instead of the track values.
This allows various sensor input stimuli to be generated.
In the synchronized operating modes the data word is
synchronized with pin SERIN as in normal operating
mode. Configuration of the various serial operating
modes is also as in normal operating mode. No stimuli
can be clocked in in No Sync Binary mode.
iC-LV has two different test modes which are activated
by connecting pin TEST to VDD. Pin MODE designates
which test mode is activated. Connected to VDD (or
not connected at all), this initiates the digital test mode;
if connected to GND the analog test mode is selected.
TP: So that the switching thresholds of the input inter-
faces (SYNM0, SYNM1, SERIN, SCLK, NDIR, NINV,
SEEN) can be measured the signals are EXORed and
output at pin NERR. To this end pin NERR is switched
as a push-pull output.