APW8871 Datasheet, PDF (18/27 Pages) Anpec Electronics Coropration – DDR4 TOTAL POWER SOLUTION (VPP/VDDQ/VTT) SYNCHRONOUS DC/DC CONVERTER for NB/MB

APW8871
Function Description (Cont.)
PWM Converter Current Limit
The current-limit circuit employs a “valley” current-sens-
ing algorithm (See Figure 3). The APW8871 uses the
internal low-side MOSFET’s R_DS(ON) of the synchronous
rectifier as a current-sensing element. If the magnitude
of the current-sense signal at LX1/LX2 pin is above the
current limit threshold individual, the PWM is not allowed
to initiate a new cycle. The actual peak current is greater
than the current limit threshold by an amount equals to
the inductor ripple current. Therefore, the exact current-
limit characteristic and maximum load capability are the
functions of the sense resistance, inductor value, and
input voltage.
The PWM controller uses the internal low-side MOSFETs
on-resistance R _DS(ON) to monitor the current for protection
against shortened outputs.
When the inductor valley current I_VALLEY is bigger than de-
vice setting I_CL, the current limit function is triggered and
internal LGATE turns on until current limit event released.
I_VALLEY can be expressed as I_OUT minus half of peak-to-
peak inductor current.
S3, S5 Control
In the DDR4 memory ap plication, it is important to keep
VPP always higher than VD DQ and VDDQ always higher
than VTT/VTTREF including both start-up and shutdown.
Th e S3 an d S5 si gna ls contro l the VPP, VDDQ, VTT,
VTTREF states an d these pi ns should be connected to
SLP_S3 and SLP_S5 sig nals res pecti vely. The tab le1
shows the truth tabl e of the S3 an d S5 pins. Wh en both
S3 and S5 are above the logic threshold voltage, the VPP,
VDDQ, VTT and VTTREF are turned on at S0 state. When
S3 is low and S5 is high, the VPP, VDDQ and VTTREF are
kept on wh ile th e VTT voltag e is d isable d and left h igh
impedance in S3 state. When both S3 and S5 are low, the
VDDQ, VTT and VTTREF are turned off and discharged to
the gro und accord ing to th e trackin g dis charg e. When
VDDQvoltage is lower than 200mV(typical), the discharge
mode changes from tracking to non-trackin g and at the
same time, it se nds a s ignal to enab le VPP disch arge
during S4/S5 state.
Table1. The Truth Table of S3 and S5 pins
STATE S3 S5 VDDQ
VTTREF
VTT
IPEAK
S0 H H
1
1
1
S3 L H
1
1
0 (high-Z)
IOUT
S4/5 L L 0 (discharge) 0 (discharge) 0 (discharge)
IVALLEY
0
Time
Figure 3. Current Limit Algorithm
VTT Sink/Source Regulator
The outputvoltage at VTT pin tracks the reference voltage
applied at VTTREF pin. Two internal N-channel MOSFETs
controlled by sep arate h igh bandwidth error amplifiers
re gul ate the ou tpu t vol tag e b y sou rci ng cu rre nt from
VLDOIN pin or sinking current to GND pin. To prevent two
pass transistors from shoot-through, a small voltage off-
set is created between the positive inputs of the two error
am plifiers . Th e VTT wi th fast resp onse fee dback lo op
keeps tracking to the VTTREF within +30 mVat all condi-
tions including fast load transient.
VPP, VDDQ and VTT Discharge Control
APW8871 discharges VPP, VDDQ, VTTREF and VTT out-
puts du ring S3 and S5 are both low. First, when S3 and
S5 are lo w, APW8871 disch arges VDDQ outpu t through
the internal VTTregulator transistors and VTT output tracks
half of VDDQ voltage during this tracking discharge. Note
that VDDQ discharge current flows via
VLDOIN to VTTGND thus VLD OIN must be conn ected to
VDDQ output.After VDDQ is discharged down to 0.2V, the
in ternal LD O i s turn ed off and th e i nte rna l d ischarge
MOSFETs thatare connected to VDDQ and VTT are turned
on. At the same time, APW8871 will send a signal to turn
on VPP di scharge device from LX2 to AGND. Therefore,
in this design rule, VPP voltage could be always guaran-
teed bigger than VDDQ voltage.
C opyright © ANPEC Electronics C orp.
18
Rev. A.1 - Sep., 2015
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