APW8871 Datasheet, PDF (16/27 Pages) Anpec Electronics Coropration – DDR4 TOTAL POWER SOLUTION (VPP/VDDQ/VTT) SYNCHRONOUS DC/DC CONVERTER for NB/MB

APW8871
Function Description
The APW8871 integrates two synchronous buck PWM
controller and high/low side power MOSFETs to gener-
ate VPP and VDDQ, two sourcing and sinking LDO linear
regulator to generate VTT and VTTREF. It provides a com-
plete power supply for DDR4 memory system in 26-pin
TQFN package. User defined output voltage is also pos-
sible and can be adjustable from 0.6V to 3.3V for VPP
terminal and SMBus 2 bits programmable 1.0V/1.1V/1.
2V/0V with maximum 500mV DAC dynamic adjustable.
Input voltage range of the VDDQ PWM converter is 4.5V to
25V and for VPP PWM converter is 3V to 5.5V. The con-
verter runs an adaptive on-time PWM operation at high-
load condition and automatically reduces frequency to
keep excellent efficiency down to several mA.
The VTT LDO can source and sink up to 0.75A peak cur-
rent with only 10µF ceramic output capacitor. VTTREF
tracks VDDQ/2 within 1% of VDDQ. VTT output tracks
VTTREF within 20 mV at no load condition while 30 mV at
full load. The LDO input can be separated from VDDQ
and optionally connected to a lower voltage by using
VLDOIN pin. This helps reducing power dissipation in
sourcing phase. The APW8871 is fully compatible to
JEDEC DDR4 specifications at S3/S5 sleep state (see
Table 1). When VPP, VDDQ and VTT are disabled, the
part has output tracking discharge function. The tracking
discharge mode discharges VDDQ and VTT outputs
through the internal LDO transistors and then VTT output
tracks half of VDDQ voltage during discharge. When VDDQ
voltage has been discharged to about 200mV, the inter-
nal discharge MOSFETs that are connected to VDDQ and
VTT are turned on. The current capability of these dis-
charge MOSFETs are limited and discharge occurs more
slowly than the tracking discharge. Furthermore, the de-
vice discharges VPP Voltage by the internal resistor
through LX2 to PGND.
Constant-On-Time PWM Controller with Input Feed-
Forward
The constant on-tim e contro l architecture is a pse udo-
fixed frequency with i nput voltage feed-forward. This ar-
chite cture re lies on the outpu t filter capacito r’s effe ctive
series resistance (ESR) to act as a current-sense resistor,
so the output ripple voltage provides the PWM ramp signal.
In PFMoperation, the high-side switch on-time controlled
by the on-time generator is determined so lely by a one-
shot whose pulse width is inverselyproportional to input
voltage and directly proportional to output voltage.In PWM
operation, the high-side switch on-time is determined by
a switchin g frequency control circuit in the on -time gen-
erator bl ock. Th e swi tchi ng freq uen cy co ntro l circu it
senses th e switching freque ncy of the high-si de switch
and ke eps regula ting it at a constant frequency in PWM
m ode. The design im proves the frequency variation and
be more outstandin g than a co nventional cons tant on-
time controller which has large switching frequencyvaria-
tion over inpu t voltage , output current an d tempera ture.
Bo th in PFM and PWM, th e o n-tim e g ene ra tor, w hi ch
sen ses in put voltage on VIN and PVCC pins, provi des
very fast on-tim e response to input line transients.
An othe r on e-sh ot se ts a m in im um off-ti me (typi ca l:
300ns). The on-time one-shot is triggered if the errorcom-
parator is high , the low-side switch curren t is below the
current-limi t thres hold, an d the mi nimum o ff-time one-
shot has timed out.
Power-On-Reset
A Power-On-Reset (POR) function is designed to prevent
wrong logic co ntrols w hen the VCC voltag e is low . The
POR function continuall y monitors the bias supply volt-
age on the VCC pin if at least one of the enable pins is set
hi gh. When the ris ing VCC voltage reaches the risi ng
POR voltage threshold (4.3Vtypical), the POR signal goes
high and the chip initiates soft-start operations. There is
alm ost no hyste resis to POR voltage thresho ld (ab out
100mV typical). When VCC vo ltage drop lower than 4.2V
(typical), the POR disables the chip.
Power Sequence and Soft- Start
Th e APW88 71 co nfo rm s to JEDEC D DR4 s equ en ce
specification. VPP must ramp at the same time or earlier
than VDD Q and VPP termi nal voltag e mus t equ al to or
higher than VDDQ at all time.APW8871 integrates digital
soft-start circuits to ramp up the output voltage ofthe con-
verter to the programmed regulation setpoint ata predict-
able slew rate. Th e slew rate of output voltag e is in ter-
nally controlled to limit the inrush current through the out-
put capacitors during soft-start process.
C opyright © ANPEC Electronics C orp.
16
Rev. A.1 - Sep., 2015
www.anpec.com.tw