APW8871 Datasheet, PDF(17/27 Page) Anpec Electronics Coropration – DDR4 TOTAL POWER SOLUTION (VPP/VDDQ/VTT) SYNCHRONOUS DC/DC CONVERTER for NB/MB

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APW8871 Datasheet, PDF (17/27 Pages) Anpec Electronics Coropration – DDR4 TOTAL POWER SOLUTION (VPP/VDDQ/VTT) SYNCHRONOUS DC/DC CONVERTER for NB/MB

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APW8871

Function Description (Cont.)

Power Sequence and Soft- Start (cont.)

The figure 2 shows VPP/VDDQ soft-start sequence.When

the S5 pin is pulled above the rising S5 threshold voltage,

the device initi ates a soft-start proces s to ramp up the

output voltage . In norma l ope ratio n, the VDDQ voltage

starts to rise up after VPP voltage has been established.

The VPP PWMconvertersoft-start interval is 0.2ms (max.);

VDDQ PWM converter s oft-start inte rval is 0.4ms (max.)

and independent of the switching frequency.

0.7ms

VCC

0.2ms

VVPP

0. 4ms

V VDDQ

VPOK

Figure 2. Soft-Start Sequence.

During soft-start stage before the POK pin is ready, the

under voltage protection is prohibited. The over voltage

and current limit protection functions are enabled. If the

output capacitor has residue voltage before startup, both

internal low-side and high-side MOSFETs are in off-state

until the internal individual digital soft start voltage equal

the VVPP/VVDDQ voltages. This will ensure the output volt-

age starts from its existing voltage level.

The VTT LDO part monitors the output current, both sourc-

ing and sinking current, and limits the maximum output

current to prevent damages during current overload or

short circuit (shorted from VTT to GND or VLDOIN)

conditions.

The VTT LDO provides a soft-start function, using the

constant current to charge the output capacitor that gives

a rapid and linear output voltage rise. If the load current is

above the current limit start-up, the VTT cannot start

successfully.

APW8871 has an independent counter for each output,

but the POK signal indicates only the status of VPP and

VDDQ and does not indicate VTT power good externally.

Power-Good Output (POK)

POK is an open-drain output and the POK comparator

continuously monitors the output voltage. POK is actively

held low in shutdown, and standby. When both PWM con-

vertersâ output voltages are greater than 90% of their tar-

get value, the internal open-drain device will be pulled

low. After 20Âµs debounce time, the POK goes high. When

one of the output voltages VPP/VDDQ outrun 125% of the

target voltage, POK signal will be pulled low with 20ms

debounce time.

Under Voltage Protection

In the process of operation, if a short-circuit occurs, the

output voltage will drop quickly. When load current is big-

ger than current limit threshold value, the output voltage

will fall out of the required regulation range. The under-

voltage continually monitors the setting output voltage

after both PWM operations to ensure startup. If a load

step is strong enough to pull the output voltage lower

than the under voltage threshold (60% of normal output

voltage), the internal UVP delay counter begins counting.

After 2Âµs debounce time, the device turns off both inter-

nal high-side and low-side MOSFETs with latched and

starts a soft-stop process to shut down the output

gradually. Toggling enable pin to low or recycling VCC

will clear the latch and bring the chip back to operation.

Over Voltage Protection (OVP)

The feedback voltage should increase over 125% of the

reference voltage due to the high-side MOSFET failure or

for other reasons, and the over voltage protection com-

parator designed with a 2Âµs noise filter will turn on the

internal low-side MOSFET. If the inductor current triggers

negative current limit, the device turns off Low-side

MOSFET for 300ns (typ.) and repeats the OVP function

action.This action actively pulls down the output voltage.

When the OVP occurs, the POK pin will pull down and

latch-off the converter. This OVP scheme only clamps the

voltage overshoot, and does not invert the output voltage

when otherwise activated with a continuously high output

from the internal low-side MOSFET driver. Itâs a common

problem for OVP schemes with a latch. Once an over-

voltage fault condition is set, toggling VCC power-on-re-

set signal can only reset it.

Rev. A.1 - Sep., 2015

www.anpec.com.tw

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