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| AAT1161 Datasheet, PDF (2/18 Pages) Advanced Analogic Technologies – 13.2V Input, 3A Step-Down Converter | |||
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SwitchRegTM
PRODUCT DATASHEET
AAT1161
13.2V Input, 3A Step-Down Converter
Pin Descriptions
Pin #
1
2
3
4, 5
6
7
8, 9
10, 11
12, EP
13
14
Symbol
FB
COMP
AGND
DGND
EN
N/C
LX
IN
PGND
AIN
LDO
Function
Output voltage feedback input. FB senses the output voltage for regulation control. For ï¬xed output ver-
sions, connect FB to the output voltage. For adjustable versions, drive FB from the output voltage through
a resistive voltage divider. The FB regulation threshold is 0.6V.
Control compensation node. In most conï¬gurations external compensation is not required. If external
compensation is required, connect a series RC network from COMP to AGND. See Compensation section.
Analog signal ground. Used for the Compensation, LDO bypass and feedback divider ground. Connect
AGND to DGND/PGND at a single point as close to the IC as possible or directly under the package ex-
posed thermal pad (EP).
Digital/Power Ground. Used for the input and enable ground. Connect DGND to AGND/PGND at a single
point as close to the IC as possible or directly under the package exposed thermal pad (EP).
Active high enable input. Drive EN high to turn on the AAT1161; drive it low to turn it off. For automatic
startup, connect EN to IN through a 4.7kΩ resistor. EN must be biased high, biased low, or driven to a
logic level by an external source. Do not let the EN pin ï¬oat when the device is powered.
No Connect. Leave ï¬oating; do not connect anything to this pin.
Power switching node. LX is the drain of the internal P-channel switch. Connect the external rectiï¬er
from LX to PGND and the external LC output ï¬lter from LX to the load.
Power source input. Connect IN to the input power source. Bypass IN to DGND with a 10μF or greater
capacitor. Connect both IN pins together as close to the IC as possible. An additional 100nF ceramic
capacitor should also be connected between the two IN pins and DGND.
Power Ground. The exposed thermal pad (EP) should be connected to board ground plane and pins 3, 4,
5 and 12 directly under the package. The ground plane should include a large exposed copper pad under
the package for thermal dissipation (see package outline).
Internal analog bias input. AIN supplies internal power to the AAT1161. Connect AIN to the input source
voltage and bypass to AGND with a 0.1μF or greater capacitor. For additional noise rejection, connect to
the input power source through a 10Ω or lower value resistor.
Internal LDO bypass node. The output voltage of the internal LDO is bypassed at LDO. The internal cir-
cuitry of the AAT1161 is powered from LDO. Do not draw external power from LDO. Bypass LDO to AGND
with a 1μF or greater capacitor.
Pin Configuration
TDFN33-14
(Top View)
FB 1
COMP 2
AGND 3
DGND 4
DGND 5
EN 6
N/C 7
14 LDO
13 AIN
12 PGND
11 IN
10 IN
9 LX
8 LX
2
www.analogictech.com
1161.2008.03.1.0
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