AAT1161 Datasheet, PDF (13/18 Pages) Advanced Analogic Technologies – 13.2V Input, 3A Step-Down Converter

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PRODUCT DATASHEET
AAT1161
13.2V Input, 3A Step-Down Converter
Part Number
M1FM3
D1FH3
SK32
SS5820
30BQ040/LSM345
B220/A
SDM100K30L
B0520WS
V_F
0.46V
0.36V
0.5V
0.475A
0.43
0.5V
0.485V
0.43V
I_F(AV)
3A
3A
3A
3A
3A
2A
1A
0.5A
V_RRM
30V
30V
20V
20V
40V
20V
30V
20V
θ_JA
80°C/W
65°C/W
60°C/W
55°C/W
46°C/W
25°C/W
426°C/W
426°C/W
T_J(MAX)
150°C
125°C
150°C
125°C
150°C
150°C
125°C
125°C
Manufacturer
Shindengen
Shindengen
MCC
Jinan Jingheng
IR/Microsemi
Diodes Inc.
Diodes Inc.
Diodes Inc.
Dimensions (mm)
2.8x1.8
4.4x2.5
7x6
4.3x3.6
7x6
4.3x3.6
1.7x1.3
1.7x1.3
Table 3: Recommended Schottky Diodes for Different Output Current Requirements.
Layout Guidance
Figure 2 is the schematic for the evaluation board. When
laying out the PC board, the following layout guideline
should be followed to ensure proper operation of the
AAT1161:
1. Exposed pad EP1 must be reliably soldered to PGND/
DGND/AGND. The exposed thermal pad should be
connected to board ground plane and pins 6, 11, 13,
and 16. The ground plane should include a large
exposed copper pad under the package for thermal
dissipation.
2. The power traces, including GND traces, the LX
traces and the VIN trace should be kept short, direct
and wide to allow large current flow. The L1 connec-
tion to the LX pins should be as short as possible.
Use several via pads when routing between layers.
3. Exposed pad pin EP2 must be reliably soldered to the
LX pins 1 and 2. The exposed thermal pad should be
connected to the board LX connection and the induc-
tor L1 and also pins 1 and 2. The LX plane should
include a large exposed copper pad under the pack-
age for thermal dissipation.
4. The input capacitors (C2 and C6) should be con-
nected as close as possible to IN (Pins 4 and 5) and
DGND (Pin 6) to get good power filtering.
5. Keep the switching node LX away from the sensitive
FB node.
6. The feedback trace for the FB pin should be separate
from any power trace and connected as closely as
possible to the load point. Sensing along a high-
current load trace will degrade DC load regulation.
The feedback resistors should be placed as close as
possible to the FB pin (Pin 9) to minimize the length
of the high impedance feedback trace.
7. The output capacitors C3, 4, and 5 and L1 should be
connected as close as possible and there should not
be any signal lines under the inductor.
8. The resistance of the trace from the load return to
the PGND (Pin 16) should be kept to a minimum.
This will help to minimize any error in DC regulation
due to differences in the potential of the internal
signal ground and the power ground.
1161.2008.03.1.0
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