AAT1171 Datasheet, PDF (18/22 Pages) Advanced Analogic Technologies – 600mA Voltage-Scaling Step-Down Converter for RF Power Amplifiers with Bypass Switch

AAT1171
600mA Voltage-Scaling Step-Down Converter
for RF Power Amplifiers with Bypass Switch
For the condition where the buck converter is at
100% duty cycle dropout, the total device dissipa-
tion reduces to:
P_TOTAL = I_O2 · R_DS(ON) + I_Q · V_IN
In bypass mode, the bypass MOSFET R_DS(ON)(bp) is
used to determine the losses. The power MOSFET
R_DS(ON) increases with decreasing input voltage
and the associated losses are a maximum at the
minimum input voltage (2.7V).
P_TOTAL = I_O2 · R_DS(ON)(bp) + I_Q · V_IN
Since the R_DS(ON), quiescent current, and switching
losses all vary with input voltage, the total losses
should be investigated over the complete input
voltage range.
After calculating the total losses, the maximum
junction temperature can be derived from the θ_JA
for the TDFN33-12 package which is typically
50°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
Layout
The suggested PCB layout for the AAT1171 is
shown in Figures 3 and 4. The following guidelines
should be used to ensure a proper layout.
1. The input capacitor (C1) should connect as
closely as possible to VIN (Pin 10) and PGND
(Pin 11).
2. C2 and L1 should be connected as closely as
possible. The connection of L1 to the LX pin
should be as short as possible.
3. The PCB trace connected to VOUT (Pins 2 and
3) is tied to the bypass path, as well as the feed-
back path for the control loop. In bypass mode,
the full load current is delivered directly from the
battery input; therefore, this trace should be suf-
ficient to handle current up to the bypass current
limit level.
4. The resistance of the trace from the load return
to PGND (Pin 11) should be kept to a minimum.
This minimizes any error in DC regulation due to
differences in the potential of the internal signal
ground and the power ground.
5. For good thermal coupling, PCB vias are required
from the pad for the TDFN exposed paddle to the
ground plane. The via diameter should be 0.3mm
to 0.33mm and positioned on a 1.2mm grid.
Figure 3: AAT1171 Evaluation Board
Top Side Layout.
18
Figure 4: AAT1171 Evaluation Board
Bottom Side Layout.
1171.2006.06.1.0