AAT1171 Datasheet, PDF (16/22 Pages) Advanced Analogic Technologies – 600mA Voltage-Scaling Step-Down Converter for RF Power Amplifiers with Bypass Switch

AAT1171
600mA Voltage-Scaling Step-Down Converter
for RF Power Amplifiers with Bypass Switch
The maximum output capacitor RMS ripple current is:
I = _RMS(MAX)
1
2·
·
3
V_OUT · (V_IN(MAX) - V_OUT)
L · FS · V_IN(MAX)
Dissipation due to the RMS current in the ceramic
output capacitor ESR is typically minimal, resulting in
less than a few degrees rise in hot-spot temperature.
Input Capacitor Selection
A 10V X5R or X7R ceramic capacitor is suggested
for the input capacitor with typical values ranging
from 4.7µF to 10µF. To estimate the required input
capacitance size, determine the acceptable input
ripple level (V_PP) and solve for C, as shown below.
The calculated value varies with input voltage and
is a maximum when V_IN is double the output volt-
age. Always examine the ceramic capacitor DC
voltage coefficient characteristics when selecting
the proper value. For example, due to the voltage
coefficient of a 10µF 6.3V X5R ceramic capacitor,
with an applied voltage of 5V DC the capacitance
decreases to 6µF.
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
C_IN =
⎛ V_PP
⎝ I_O
- ESR^⎞⎠ · F_S
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
=
1
4
V_IN = 2 · V_O
1
C_IN(MIN) = _{⎛ VPP}
⎝ I_O
- ESR^⎞⎠ · 4 · F_S
The maximum input capacitor RMS current is:
I_RMS = I_O ·
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
The input capacitor RMS ripple current varies with
the input and output voltage and will always be less
than or equal to half of the total DC load current.
V_O
V_IN
· ^⎛⎝1 -
V_O ⎞
V_IN ⎠
=
D · (1 - D) =
0.5² = ¹
2
for V_IN = 2 · V_O
I = _RMS(MAX)
I_O
2
The term
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
appears in both the input
voltage ripple and input capacitor RMS current
equations and is a maximum when V_IN is twice V_o;
therefore, the input voltage ripple and the input
capacitor RMS current ripple are a maximum at
50% duty cycle.
The input capacitor provides a low impedance loop
for the edges of pulsed current drawn by the
AAT1171. Low ESR/ESL X7R and X5R ceramic
capacitors are ideal for this function. To minimize
stray inductance, the capacitor should be placed as
closely as possible to the IC. This keeps the high
frequency content of the input current localized,
minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C1)
can be seen in the evaluation board layout in
Figure 3.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the
evaluation board input voltage pins. The inductance
of these wires, along with the low-ESR ceramic input
capacitor, can create a high Q network that may
affect converter performance. This problem often
becomes apparent in the form of excessive ringing
in the output voltage during load transients with
errors in loop phase and gain measurements.
Since the inductance of a short PCB trace feeding
the input voltage is significantly lower than the
power leads from the bench power supply, most
applications do not exhibit this problem.
16
1171.2006.06.1.0