AAT1130 Datasheet, PDF (14/19 Pages) Advanced Analogic Technologies – 2.5MHz 500mA Step-Down DC/DC Converter

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PRODUCT DATASHEET
AAT1130
2.5MHz 500mA Step-Down DC/DC Converter
Feedback Resistor Selection
Resistors R1 and R2 of Figure 4 program the output to
regulate at a voltage higher than 0.6V. To limit the bias
current required for the external feedback resistor string
while maintaining good noise immunity, the minimum
suggested value for R2 is 59kΩ. Although a larger value
will further reduce quiescent current, it will also increase
the impedance of the feedback node, making it more
sensitive to external noise and interference. Table 2
summarizes the resistor values for various output volt-
ages with R2 set to either 59kΩ for good noise immunity
or 221kΩ for reduced no load input current.
R1 =
V_OUT
V_FB
-1
· R2 =
1.5V
0.6V ^{- 1 · 59kΩ = 88.5kΩ}
The AAT1130, combined with an external feedforward
capacitor (C3 in Figure 4), delivers enhanced transient
response for extreme pulsed load applications. The addi-
tion of the feedforward capacitor typically requires a
larger output capacitor C1 for stability.
V_OUT (V)
0.9
1
1.1
1.2
1.3
1.4
1.5
1.8
R2 = 59kΩ
R1 (kΩ)
29.4
39.2
49.9
59.0
68.1
78.7
88.7
118
R2 = 221kΩ
R1 (kΩ)
113
150
187
221
261
301
332
442
Table 2: Feedback Resistor Values.
Thermal Calculations
There are three types of losses associated with the
AAT1130 step-down converter: switching losses, conduc-
tion losses, and quiescent current losses. Conduction
losses are associated with the R_DS(ON) characteristics of
the power output switching devices. Switching losses are
dominated by the gate charge of the power output
switching devices. At full load, assuming continuous con-
duction mode (CCM), a simplified form of the losses is
given by:
P_TOTAL =
I_O2 · (R_DS(ON)H · V_O + R_DS(ON)L · [V_IN - V_O])
V_IN
+ (t_sw · F_S · I_O + I_Q) · V_IN
I_Q is the step-down converter quiescent current. The
term t_sw is used to estimate the full load step-down con-
verter switching losses. For the condition where the
step-down converter is in dropout at 100% duty cycle,
the total device dissipation reduces to:
P_TOTAL = I_O2 · R_DS(ON)H + I_Q · V_IN
Since R_DS(ON), quiescent current, and switching losses all
vary with input voltage, the total losses should be inves-
tigated over the complete input voltage range. Given the
total losses, the maximum junction temperature can be
derived from the θ_JA for the SC70JW-10 package which
is 160°C/W.
T_J(MAX) = P_TOTAL · Θ_JA + T_AMB
Layout
The suggested PCB layout for the AAT1130 is shown in
Figures 1, 2, and 3. The following guidelines should be
used to help ensure a proper layout:
1. The input capacitor (C1) should connect as closely as
possible to VCC/VP (pins 3 and 4) and PGND/GND
(pins 7-10 for adjustable output voltage and pins
6-10 for fixed output voltage).
2. C1 and L1 should be connected as closely as possi-
ble. The connection of L1 to the LX (pin 5) should be
as short as possible.
3. The feedback trace or FB (pin 1 for adjustable output
voltage) should be separate from any power trace
and connect as closely as possible to the load point.
Sensing along a high current load trace will degrade
DC load regulation. If external feedback resistors are
used, they should be placed as closely as possible to
the FB (pin 1 for adjustable output voltage) to mini-
mize the length of the high impedance feedback
trace.
4. The resistance of the trace from the load return to
the PGND/GND (pins 7-10 for adjustable output volt-
age and pins 6-10 for fixed output voltage) should
be kept to a minimum. This will help to minimize any
error in DC regulation due to differences in the
potential of the internal signal ground and the power
ground.
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