AAT1130 Datasheet, PDF (13/19 Pages) Advanced Analogic Technologies – 2.5MHz 500mA Step-Down DC/DC Converter

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PRODUCT DATASHEET
AAT1130
2.5MHz 500mA Step-Down DC/DC Converter
Applications Information
Inductor Selection
The step-down converter uses valley current mode con-
trol with slope compensation to maintain stability for
duty cycles greater than 50%. The output inductor value
must be selected so the inductor current down slope
meets the internal slope compensation requirements.
Table 1 displays suggested inductor values for various
output voltages.
Manufacturer’s specifications list both the inductor DC
current rating, which is a thermal limitation, and the
peak current rating, which is determined by the satura-
tion characteristics. The inductor should not show any
appreciable saturation under normal load conditions.
Some inductors may meet the peak and average current
ratings yet result in excessive losses due to a high DCR.
Always consider the losses associated with the DCR and
its effect on the total converter efficiency when selecting
an inductor. See Table 3 for suggested inductor values
and vendors.
Configuration
Adjustable and Fixed
Output Voltage
Output
Voltage
1V, 1.2V, 1.3V
1.5V, 1.8V
Inductor
Value
1.0μH to 1.5μH
1.5μH to 2.2μH
Table 1: Inductor Values for Specific Output
Voltages.
Input Capacitor
Select a 4.7μF to 10μF X7R or X5R ceramic capacitor for
the input. Always examine the ceramic capacitor DC
voltage coefficient characteristics when selecting the
proper value. For example, the capacitance of a 10μF,
6.3V, X5R ceramic capacitor with 5.0V DC applied is
actually about 6μF.
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the AAT1130. Low
ESR/ESL X7R and X5R ceramic capacitors are ideal for
this function. To minimize stray inductance, the capaci-
tor should be placed as closely as possible to the IC. This
keeps the high frequency content of the input current
localized, minimizing EMI and input voltage ripple.
The proper placement of the input capacitor (C1) can be
seen in the evaluation board layouts in Figures 4, 5, 6,
and 7.
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the evalu-
ation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result.
Since the inductance of a short PCB trace feeding the
input voltage is significantly lower than the power leads
from the bench power supply, most applications do not
exhibit this problem. In applications where the input
power source lead inductance cannot be reduced to a
level that does not affect the converter performance, a
high ESR tantalum or aluminum electrolytic should be
placed in parallel with the low ESR, ESL bypass ceram-
ic. This dampens the high Q network and stabilizes the
system.
Output Capacitor
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 4.7μF to
10μF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple.
The internal voltage loop compensation also limits the
minimum output capacitor value to 4.7μF. This is due to
its effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
C_FF
R1
FB
R2
Figure 1: AAT1130 External Resistor
Output Voltage Programming.
1130.2008.08.1.1
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