AAT2860 Datasheet, PDF (13/23 Pages) Advanced Analogic Technologies – Backlight/Flash LED Driver and Multiple LDO Lighting Management Unit

PRODUCT DATASHEET
AAT2860
ChargePump^TM Backlight/Flash LED Driver and Multiple LDO Lighting Management Unit
A STOP condition, as shown in Figure 2, is when SCL
changes from low to high followed after the STOP condi-
tion setup time (t_{SU_STO}), by the SDA low-to-high transi-
tion. The master does not issue an ACK and releases
both the SCL and SDA line.
Transferring Data
Addresses and data are sent with the most significant bit
transmitted first and the least significant bit transmitted
last. After each address or data transmission, the target
device transmits an ACK signal to indicate that it has
received the transmission. The ACK signal is generated
by the target after the master releases the SDA data line
by driving the SDA data line low.
I²C Serial Programming Registers
The AAT2860’s I²C programming registers are listed in
Table 1. There are six registers, two for backlight LED
configuration/control, one for flash/lamp LED configura-
tion/control, and two registers to control the three LDOs.
For the remainder of this document the superscript "¹"
signifies the power on reset (POR) value of a register, the
superscript "²" signifies the default value of "1" for a par-
ticular bit of a register, and the superscript "³" signifies
"Don't Care" or "Reserved."
LDO Control Registers, REG0 and REG1
Configuring and controlling the AAT2860-x’s three LDO
regulators is performed by applying a low-to-high strobe
on the LDO_SEL pin and then programming registers
REG0 and REG1 over the I²C compatible interface. Two
4-bit nibbles in REG0 set the output voltages for LDOA
and LDOB to one of 16 levels. In REG1, the most-signif-
icant nibble programs LDOC’s output voltage while the
least-significant 4-bit nibble controls each LDO’s ON/OFF
status. Upon power-on reset (POR), all three LDO out-
puts are held to 0V or AGND. The programmed LDO
output voltage will only appear after writing a “1” to
each or all REG1[D3:D1] locations. If a high-to-low tran-
sition is applied to the LDO_SEL pin, all three LDO out-
puts are forced to 0V and the register contents are reset
to their POR values. The available LDO output voltages
are shown in Table 2.
REG0
REG1
REG2
REG3
REG4
REG5
D7
LDOA[3]
LDOC[3]
X³
FLOOR[1]
F_HI[3]²
X³
D6
LDOA[2]
LDOC[2]
MEQS²
FLOOR[0]
F_HI[2]²
X³
D5
LDOA[1]
LDOC[1]
MAIN_ON
SUB_ON
F_HI[1]
X³
D4
LODA[0]
LODC[0]
WM[4]
WS[4]
F_HI[0]
X³
D3
LDOB[3]
ENLDO_C
WM[3]
WS[3]
F_TIME[1]
X³
D2
LDOB[2]
ENLDO_B
WM[2]
WS[2]
F_TIME[0]
X³
D1
LDOB[1]
ENLDO_A
WM[1]
WS[1]
F_LO[1]²
NOFADE_M²
D0
LODB[0]
X³
WM[0]
WS[0]
F_LO[0]²
NOFADE_S²
Table 1: AAT2860-x Configuration/Control Register Allocation.
LDOx[4:0]
0000¹
0001
0010
0011
0100
0101
0110
0111
LDO V_OUT [A/B/C] (V)
1.5¹
1.6
1.7
1.8
1.9
2.0
2.1
2.2
LDOx[4:0]
1000
1001
1010
1011
1100
1101
1110
1111
Table 2: LDO[A:C] Output Voltage Control Data
LDO V_OUT [A/B/C] (V)
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
1. Denotes the default (power-on-reset) value.
2. Denotes default value is "1" or ON.
3. Don't Care or Reserved.
2860.2008.05.1.0
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