AAT1162_08 Datasheet, PDF (13/18 Pages) Advanced Analogic Technologies – 12V, 1.5A Step-Down DC/DC Converter

SwitchReg^TM
Output Capacitor Selection
The output capacitor is required to keep the output volt-
age ripple small and to ensure regulation loop stability.
The output capacitor must have low impedance at the
switching frequency. Ceramic capacitors with X5R or
X7R dielectrics are recommended due to their low ESR
and high ripple current. The output ripple V_OUT is deter-
mined by:
ΔV_OUT ≤
V_OUT · (V_IN - V_OUT) _·
V_IN · F_OSC · L
⎛⎝_{ESR +}
1
⎞
8 · F_OSC · C_OUT⎠
The output capacitor limits the output ripple and pro-
vides holdup during large load transitions. A 10μF to
47μF X5R or X7R ceramic capacitor typically provides
sufficient bulk capacitance to stabilize the output during
large load transitions and has the ESR and ESL charac-
teristics necessary for low output ripple. The output volt-
age droop due to a load transient is dominated by the
capacitance of the ceramic output capacitor. During a
step increase in load current, the ceramic output capac-
itor alone supplies the load current until the loop
responds. Within two or three switching cycles, the loop
responds and the inductor current increases to match
the load current demand. The relationship of the output
voltage droop during the three switching cycles to the
output capacitance can be estimated by:
C_OUT
=
3 · ΔI_LOAD
V_DROOP · F_OSC
Once the average inductor current increases to the DC
load level, the output voltage recovers. The above equa-
tion establishes a limit on the minimum value for the
output capacitor with respect to load transients. The
internal voltage loop compensation also limits the mini-
mum output capacitor value to 22μF. This is due to its
effect on the loop crossover frequency (bandwidth),
phase margin, and gain margin. Increased output capac-
itance will reduce the crossover frequency with greater
phase margin.
PRODUCT DATASHEET
AAT1162
12V, 1.5A Step-Down DC/DC Converter
The maximum output capacitor RMS ripple current is
given by:
I = _RMS(MAX)
1
2·
·
3
V_OUT · (V_IN(MAX) - V_OUT)
L · F_OSC · V_IN(MAX)
Dissipation due to the RMS current in the ceramic output
capacitor ESR is typically minimal, resulting in less than
a few degrees rise in hot-spot temperature.
Compensation
The AAT1162 step-down converter uses peak current
mode control with slope compensation scheme to main-
tain stability with lower value inductors for duty cycles
greater than 50%. The regulation feedback loop in the
IC is stabilized by the components connected to the
COMP pin, as shown in Figure 1.
To optimize the compensation components, the following
equations can be used. The compensation resistor R_COMP
(R5) is calculated using the following equation:
R_COMP (R5)=
2πV_OUT · C_OUT · F_OSC
10G_EA · G_COMP · V_FB
Where V_FB = 0.6V, G_COMP = 40.1734 and G_EA = 9.091 ·
10^-5.
F_OSC is the switching frequency and C_OUT is based on the
output capacitor calculation. The C_COMP value can be
determined from the following equation:
4
C_COMP
(C7)
=
2πR_COMP
(R5)
·
⎛F_OSC⎞
⎝ 10 ⎠
The feed forward capacitor CFF (C1) provides faster
transient response for pulsed load applications. The
addition of the feed forward capacitor typically requires
a larger output capacitor C1 for stability. Larger C1 val-
ues reduce overshoot and undershoot during startup
and line/load changes. The CFF value can be from 100pF
to 470pF, but do not exceed 470pF to maintain stable
operation.
1162.2008.01.1.3
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