AAT1162_08 Datasheet, PDF (12/18 Pages) Advanced Analogic Technologies – 12V, 1.5A Step-Down DC/DC Converter

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PRODUCT DATASHEET
AAT1162
12V, 1.5A Step-Down DC/DC Converter
Manufacturer
Sumida
Sumida
Coilcraft
Cooper Bussman
Wurth
Part Number
CDRH103RNP-2R2N
CDR7D43MNNP-3R7NC
MSS1038-382NL
DR73-4R7-R
7440530047
L (μH)
2.2
3.7
3.8
4.7
4.7
Max DCR
(mΩ)
16.9
18.9
13
29.7
38
Rated DC
Current (A)
5.10
4.3
4.25
3.09
2.40
Table 2: Typical Surface Mount Inductors.
Size WxLxH
(mm)
10.3x10.5x3.1
7.6x7.6x4.5
10.2x7.7x3.8
6.0x7.6x3.55
5.8x5.8x2.8
To estimate the required input capacitor size, determine
the acceptable input ripple level (V_PP) and solve for C.
The calculated value varies with input voltage and is a
maximum when V_IN is double the output voltage.
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
C_IN =
⎛ V_PP
⎝ I_O
- ESR^⎞⎠ · F_OSC
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
=
1
4
for
V_IN
=
2
·
V_O
1
C_IN(MIN) = _{⎛ VPP}
⎝ I_O
- ESR^⎞⎠ · 4 · F_OSC
Always examine the ceramic capacitor DC voltage coef-
ficient characteristics when selecting the proper value.
For example, the capacitance of a 10μF, 16V, X5R ceram-
ic capacitor with 12V DC applied is actually about
8.5μF.
The maximum input capacitor RMS current is:
I_RMS = I_O ·
V_O
V_IN
·
⎛⎝_{1 -}
V_O ⎞
V_IN ⎠
The input capacitor RMS ripple current varies with the
input and output voltage and will always be less than or
equal to half of the total DC load current:
V_O
V_IN
· ^⎛⎝1 -
V_O ⎞
V_IN ⎠
=
D · (1 - D) =
0.5²
=
1
2
for V_IN = 2 · V_O
I = _RMS(MAX)
I_O
2
The term
VO
VIN
·
⎛⎝_{1 -}
VO ⎞
VIN ⎠
appears in both the input voltage
ripple and input capacitor RMS current equations and is
at maximum when V_O is twice V_IN. This is why the input
voltage ripple and the input capacitor RMS current ripple
are a maximum at 50% duty cycle. The input capacitor
provides a low impedance loop for the edges of pulsed
current drawn by the AAT1162. Low ESR/ESL X7R and
X5R ceramic capacitors are ideal for this function. To
minimize stray inductance, the capacitor should be
placed as closely as possible to the IC. This keeps the
high frequency content of the input current localized,
minimizing EMI and input voltage ripple. The proper
placement of the input capacitor (C6) can be seen in the
evaluation board layout in Figure 3. Additional noise fil-
tering for proper operation is accomplished by adding a
small 0.1μF capacitor on the IN pins (C2).
A laboratory test set-up typically consists of two long
wires running from the bench power supply to the eval-
uation board input voltage pins. The inductance of these
wires, along with the low-ESR ceramic input capacitor,
can create a high Q network that may affect converter
performance. This problem often becomes apparent in
the form of excessive ringing in the output voltage dur-
ing load transients. Errors in the loop phase and gain
measurements can also result. Since the inductance of a
short PCB trace feeding the input voltage is significantly
lower than the power leads from the bench power sup-
ply, most applications do not exhibit this problem. In
applications where the input power source lead induc-
tance cannot be reduced to a level that does not affect
the converter performance, a high ESR tantalum or alu-
minum electrolytic should be placed in parallel with the
low ESR, ESL bypass ceramic. This dampens the high Q
network and stabilizes the system.
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1162.2008.01.1.3