AAT2315_07 Datasheet, PDF (10/22 Pages) Advanced Analogic Technologies – Dual 600mA Step-Down Converter with Synchronization

Functional Block Diagram
FB1
VCC
AAT2513
Dual 600mA Step-Down
Converter with Synchronization
VIN1
EN1
AGND
MODE/SYNC
PS
FB
EN2
Err.
Amp.
Comp
Voltage
Reference
Control
Logic
Oscillator
DH
Logic
DL
Err.
Amp.
Comp.
Voltage
Reference
Control
Logic
DH
Logic
DL
LX1
PGND1
VIN2
LX2
PGND2
Functional Description
The AAT2513 is a peak current mode pulse width
modulated (PWM) converter with internal compen-
sation. Each channel has independent input,
enable, feedback, and ground pins with a 1.7MHz
clock. Both converters operate in either a fixed fre-
quency (PWM) mode or a more efficient light load
(LL) mode. A phase shift pin programs the convert-
ers to operate in phase or 180° out of phase. The
converter can also be synchronized to an external
clock during PWM operation.
The input voltage range is 2.7V to 5.5V. An exter-
nal resistive divider as shown in Figure 1 programs
the output voltage up to the input voltage. The con-
verter MOSFET power stage is sized for 600mA
load capability with up to 96% efficiency. Light load
efficiency is up to 90% at a 1mA load.
10
Soft Start / Enable
The AAT2513 soft start control prevents output volt-
age overshoot and limits inrush current when either
the input power or the enable input is applied.
When pulled low, the enable input forces the con-
verter into a low power non-switching state with a
bias current of less than 1µA.
Low Dropout Operation
For conditions where the input voltage drops to the
output voltage level, the converter duty cycle
increases to 100%. As the converter approaches
the 100% duty cycle, the minimum off time initially
forces the high side on time to exceed the 1.7MHz
clock cycle and reduce the effective switching fre-
quency. Once the input drops below the level
where the converter can regulate the output, the
high side P-channel MOSFET is enabled continu-
ously for 100% duty cycle. At 100% duty cycle the
output voltage tracks the input voltage minus the
I*R drop of the high side P-channel MOSFET.
2513.2007.04.1.1